ICPP 1983:
Columbus,
Ohio,
USA
International Conference on Parallel Processing, ICPP'83, Columbus, Ohio, USA, August 1983.
IEEE Computer Society 1983 BibTeX
Session 2A:
Multistage Network Performance
Session 2B:
Numerical Algorithms I
Session 3A:
Multistage Networks
- Bharat Deep Rathi, Sanjay R. Deshpande, Matthew Sejnowski, Don Walker, Roy M. Jenevein, G. Jack Lipovski, James C. Browne:
Specification and Implementation of an Integrated Packet Communication Facility for an Array Computer.
51-58 BibTeX
- Sanjay Dhar, Mark A. Franklin, Donald F. Wann:
Timing Control of VLSI Based NlogN and Crossbar Networks.
59-64 BibTeX
- David C. H. Lee, John Paul Shen:
Easily-Testable (N, K) Shuffle/Exchange Networks.
65-70 BibTeX
- Krishnan Padmanabhan, Duncan H. Lawrie:
Fault Tolerance Schemes in Shuffle-Exchange Type Interconnection Networks.
71-75 BibTeX
- Suresh C. Kothari, S. Lakshmivarahan:
A Condition Known to be Sufficient for Rearrangeability of the Benes Class of Interconnection Networks with 2x2 Switches Is Also Necessary.
76-78 BibTeX
Session 3B:
Numerical Algorithms II
- Ming-Yang Chern, Tadao Murata:
A Fast Algorithm for Concurrent LU Decomposition and Matrix Inversion.
79-86 BibTeX
- Qing-Shi Gao, Rong-Quan Wang:
Vector Computer for Sparse Matrix Operations.
87-89 BibTeX
- Ming-Yang Chern, Tadao Murata:
Efficient Matrix Multiplications on a Concurrent Data-Loading Array Processor.
90-94 BibTeX
- Tsutomu Hoshino, Tomonori Shirakawa, Takeshi Kamimura, Takahisa Kageyama, Kiyo Takenouchi, Hidehiko Abe, Satoshi Sekiguchi, Yoshio Oyanagi, Toshio Kawai:
Highly Parallel Processor Array "PAX" for Wide Scientific Applications.
95-105 BibTeX
Session 4A:
Network Connection Capabilities
Session 4B:
Special Purpose Systems
Session 5A:
Node-to-Node Networks
Session 5B:
Non-Numerical Algorithms I
Session 6A:
Tree Structured Systems
Session 6B:
Non-Numerical Algorithms II
Session 7A:
Parallel Programming and Languages
Session 7B:
Images and Speech
Session 8A:
Expressing Parallelism
Session 8B:
Database Machines/Signal Processing
Session 9A:
Data Flow
Session 9B:
Simulation/Operating Systems
Session 10A:
Models
Session 10B:
Scheduling Resources
Session 11A:
System Performance
Session 11B:
VLSI Processor Arrays
Session 12A:
Computer Architectures
Session 12B:
Associative Processing/Distributed Systems
Session 13A:
Multiprocessor Systems
- Wong-Hua Lee, Miroslaw Malek:
MOPAC: A Partitionable and Reconfigurable Multicomputer Array.
506-510 BibTeX
- Hans-Joerg Brundiers, Richard E. Buehrer, Hansmartin Friess, Milan Tadian:
The Multiprocessor EMPRESS: A Useful Tool for Studying Parallelization Concepts.
511-513 BibTeX
- Creve Maples, Daniel Weaver, Douglas Logan, William Rathbun:
Performance of a Modular Interactive Data Analysis System (MIDAS).
514-519 BibTeX
- Nikitas J. Dimopoulos:
The Homogeneous Multiprocessor Architecture : Structure and Performance Analysis.
520-523 BibTeX
- Daniel Gajski, David J. Kuck, Duncan H. Lawrie, Ahmed H. Sameh:
Cedar : A Large Scale Multiprocessor.
524-529 BibTeX
Session 13B:
Pipeling
Copyright © Sat May 16 23:20:58 2009
by Michael Ley (ley@uni-trier.de)
