Po-Ching Hsu

2005
2	EE	Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Shianling Wu, Jonhson Guo: At-Speed Logic BIST Architecture for Multi-Clock Designs. ICCD 2005: 475-478
1996
1	EE	Po-Ching Hsu, Sying-Jyan Wang: Testing And Diagnosis Of Board Interconnects In Microprocessor-Based Systems. Asian Test Symposium 1996: 56-61

Coauthor Index

1	Jonhson Guo	[2]
2	Laung-Terng Wang	[2]
3	Sying-Jyan Wang	[1]
4	Xiaoqing Wen	[2]
5	Shianling Wu	[2]

Colors in the list of coauthors