Shekhar Borkar
List of publications from the DBLP Bibliography Server - FAQ
2008 | ||
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39 | EE | Ruchir Puri, William H. Joyner, Shekhar Borkar, Ty Garibay, Jonathan Lotz, Robert K. Montoye: Custom is from Venus and synthesis from Mars. DAC 2008: 992 |
2007 | ||
38 | EE | Shekhar Borkar: Thousand Core ChipsA Technology Perspective. DAC 2007: 746-749 |
37 | EE | Shekhar Borkar, Norman P. Jouppi, Per Stenström: Microprocessors in the era of terascale integration. DATE 2007: 237-242 |
36 | EE | Shekhar Borkar, William J. Dally: Future of on-chip interconnection architectures. ISLPED 2007: 122 |
35 | EE | Yatin Hoskote, Sriram Vangal, Arvind Singh, Nitin Borkar, Shekhar Borkar: A 5-GHz Mesh Interconnect for a Teraflops Processor. IEEE Micro 27(5): 51-61 (2007) |
2006 | ||
34 | EE | Shekhar Y. Borkar, Robert W. Brodersen, Jue-Hsien Chern, Eric Naviasky, D. Saias, Charles Sodini: Tomorrow's analog: just dead or just different? DAC 2006: 709-710 |
33 | EE | Shekhar Borkar: Electronics beyond nano-scale CMOS. DAC 2006: 807-808 |
32 | EE | Shekhar Borkar: Introduction to panel discussion Probabilistic & statistical design - the wave of the future. VLSI-SoC 2006 |
31 | EE | Shekhar Borkar: Tackling variability and reliability challenges. IEEE Design & Test of Computers 23(6): 520 (2006) |
30 | EE | Chris H. Kim, Kaushik Roy, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar: A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits. IEEE Trans. VLSI Syst. 14(6): 646-649 (2006) |
2005 | ||
29 | EE | Chris H. Kim, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar, Kaushik Roy: Self Calibrating Circuit Design for Variation Tolerant VLSI Systems. IOLTS 2005: 100-105 |
28 | EE | Steven Hsu, Amit Agarwal, Kaushik Roy, Ram Krishnamurthy, Shekhar Y. Borkar: An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS. ISLPED 2005: 103-106 |
27 | EE | Shekhar Y. Borkar: VLSI Design Challenges for Gigascale Integration. VLSI Design 2005: 27- |
26 | EE | Shekhar Y. Borkar: Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation. IEEE Micro 25(6): 10-16 (2005) |
2004 | ||
25 | EE | Richard Goldman, Kurt Keutzer, Clive Bittlestone, Ahsan Bootehsaz, Shekhar Y. Borkar, E. Chen, Louis Scheffer, Chandramouli Visweswariah: Is statistical timing statistically significant? DAC 2004: 498 |
24 | EE | Shekhar Borkar, Tanay Karnik, Vivek De: Design and reliability challenges in nanometer technologies. DAC 2004: 75 |
23 | Shekhar Y. Borkar: Microarchitecture and Design Challenges for Gigascale Integration. MICRO 2004: 3 | |
2003 | ||
22 | EE | Shekhar Borkar, Tanay Karnik, Siva Narendra, James Tschanz, Ali Keshavarzi, Vivek De: Parameter variations and impact on circuits and microarchitecture. DAC 2003: 338-342 |
21 | EE | Andrew B. Kahng, Shekhar Borkar, John M. Cohn, Antun Domic, Patrick Groeneveld, Louis Scheffer, Jean-Pierre Schoellkopf: Nanometer design: place your bets. DAC 2003: 546-547 |
20 | EE | Bhaskar Chatterjee, Manoj Sachdev, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar: Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies. ISLPED 2003: 122-127 |
19 | Shekhar Borkar: Exponential Challenges, Exponential Rewards - The future of Moore's Law. VLSI-SOC 2003: 2 | |
18 | EE | Shekhar Borkar: Getting Gigascale Chips: Challenges and Opportunities in Continuing Moore's Law. ACM Queue 1(7): 26-33 (2003) |
2002 | ||
17 | EE | Tanay Karnik, Yibin Ye, James Tschanz, Liqiong Wei, Steven M. Burns, Venkatesh Govindarajulu, Vivek De, Shekhar Borkar: Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors. DAC 2002: 486-491 |
16 | EE | George Sery, Shekhar Borkar, Vivek De: Life is CMOS: why chase the life after? DAC 2002: 78-83 |
15 | EE | Tanay Karnik, Shekhar Borkar, Vivek De: Sub-90nm technologies: challenges and opportunities for CAD. ICCAD 2002: 203-206 |
14 | EE | Siva Narendra, Vivek De, Shekhar Borkar, Dimitri Antoniadis, Anantha Chandrakasan: Full-chip sub-threshold leakage power prediction model for sub-0.18 µm CMOS. ISLPED 2002: 19-23 |
13 | EE | Fatih Hamzaoglu, Yibin Ye, Ali Keshavarzi, Kevin Zhang, Siva Narendra, Shekhar Borkar, Mircea R. Stan, Vivek De: Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache. IEEE Trans. VLSI Syst. 10(2): 91-95 (2002) |
2001 | ||
12 | EE | Ram Krishnamurthy, Mark Anders, K. Soumyanath, Shekhar Borkar: Leakage control and tolerance challenges for sub-0.1µm microprocessor circuits. ACM Great Lakes Symposium on VLSI 2001: 43-44 |
11 | EE | Shekhar Borkar: Low power design challenges for the decade (invited talk). ASP-DAC 2001: 293-296 |
10 | EE | Andrew B. Kahng, Bing J. Sheu, Nancy Nettleton, John M. Cohn, Shekhar Borkar, Louis Scheffer, Ed Cheng, Sang Wang: Panel: Is Nanometer Design Under Control? DAC 2001: 591-592 |
9 | EE | James Tschanz, Siva Narendra, Zhanping Chen, Shekhar Borkar, Manoj Sachdev, Vivek De: Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors. ISLPED 2001: 147-152 |
8 | EE | Siva Narendra, Vivek De, Dimitri Antoniadis, Anantha Chandrakasan, Shekhar Borkar: Scaling of stack effect and its application for leakage reduction. ISLPED 2001: 195-200 |
7 | EE | Ali Keshavarzi, Sean Ma, Siva Narendra, B. Bloechel, K. Mistry, T. Ghani, Shekhar Borkar, Vivek De: Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs. ISLPED 2001: 207-212 |
6 | EE | Atila Alvandpour, Ram Krishnamurthy, K. Soumyanath, Shekhar Borkar: A low-leakage dynamic multi-ported register file in 0.13mm CMOS. ISLPED 2001: 68-71 |
2000 | ||
5 | EE | Vivek De, Shekhar Borkar: Low power and high performance design challenges in future technologies. ACM Great Lakes Symposium on VLSI 2000: 1-6 |
1999 | ||
4 | EE | Vivek De, Shekhar Borkar: Technology and design challenges for low power and high performance. ISLPED 1999: 163-168 |
3 | EE | Ali Keshavarzi, Siva Narendra, Shekhar Borkar, Charles F. Hawkins, Kaushik Roy, Vivek De: Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's. ISLPED 1999: 252-254 |
1990 | ||
2 | Shekhar Borkar, Robert Cohn, George W. Cox, Thomas R. Gross, H. T. Kung, Monica S. Lam, Margie Levine, Brian Moore, Wire Moore, Craig Peterson, Jim Susman, Jim Sutton, John Urbanski, Jon A. Webb: Supporting Systolic and Memory Communciation in iWarp. ISCA 1990: 70-81 | |
1988 | ||
1 | EE | Shekhar Borkar, Robert Cohn, George W. Cox, Sha Gleason, Thomas R. Gross: Warp: an integrated solution of high-speed parallel computing. SC 1988: 330-339 |