| 2008 |
|---|
| 5 | EE | Li-Pu Chuang,
Ming-Hung Chang,
Po-Tsang Huang,
Chih-Hao Kan,
Wei Hwang:
A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop.
ISCAS 2008: 3342-3345 |
| 4 | EE | Ming-Hung Chang,
Li-Pu Chuang,
I-Ming Chang,
Wei Hwang:
A 300-mV 36-muW multiphase dual digital clock output generator with self-calibration.
SoCC 2008: 97-100 |
| 2007 |
|---|
| 3 | EE | Ming-Hung Chang,
Zong-Xi Yang,
Wei Hwang:
A 1.9mW Portable ADPLL-based Frequency Synthesizer for High Speed Clock Generation.
ISCAS 2007: 1137-1140 |
| 2 | EE | Ming-Hung Chang,
Hung-Ching Lu,
Cheng-Hung Tsai:
Fuzzy neural network design with switching strategy for permanent-magnet synchronous motor speed controller.
SMC 2007: 882-887 |
| 1 | EE | Shien-Kuei Liaw,
Ming-Hung Chang,
Chun-Jung Wang,
Yi-Tseng Lin:
Reconfigurable Optical Add/Drop Multiplexer with 8.0 dB Net Gain Using Dual-Pass Amplified Scheme.
IEICE Transactions 90-B(8): 2016-2021 (2007) |
