Tad Kwasniewski

2008
3	EE	Bangli Liang, Tad Kwasniewski, Dianyong Chen: A 42-Gb/s Decision Circuit in 0.13µm CMOS. CNSR 2008: 339-342
2	EE	Miao Li, Tad Kwasniewski, Shoujun Wang: A 0.18-µm CMOS clock and data recovery circuit with reference-less dual loops. ISCAS 2008: 2358-2361
1	EE	Ramin Shariat-Yazdi, Tad Kwasniewski: A multi-mode sphere detector architecture for WLAN applications. SoCC 2008: 155-158

Coauthor Index

1	Dianyong Chen	[3]
2	Miao Li	[2]
3	Bangli Liang	[3]
4	Ramin Shariat-Yazdi	[1]
5	Shoujun Wang	[2]

Colors in the list of coauthors