| 2003 |
|---|
| 10 | EE | Sergej Sawitzki,
Rainer G. Spallek:
Architecture Template and Design Flow to Support Applications Parallelism on Reconfigurable Platforms.
FPL 2003: 1119-1122 |
| 2002 |
|---|
| 9 | EE | Steffen Köhler,
Jens Braunes,
Sergej Sawitzki,
Rainer G. Spallek:
Improving Code Efficiency for Reconfigurable VLIW Processors.
IPDPS 2002 |
| 2001 |
|---|
| 8 | EE | John Dielissen,
Jef L. van Meerbergen,
Marco Bekooij,
Françoise Harmsze,
Sergej Sawitzki,
Jos Huisken,
Albert van der Werf:
Power-efficient layered turbo decoder processor.
DATE 2001: 246-251 |
| 7 | EE | Sergej Sawitzki,
Steffen Köhler,
Rainer G. Spallek:
Prototyping Framework for Reconfigurable Processors.
FPL 2001: 6-16 |
| 2000 |
|---|
| 6 | EE | Sergej Sawitzki,
Rainer G. Spallek,
Jens Schönherr,
Bernd Straube:
Formal Verification for Microprocessors with Extendable Instruction Set.
ASAP 2000: 47-55 |
| 5 | EE | Sergej Sawitzki,
Jens Schönherr,
Rainer G. Spallek,
Bernd Straube:
Formal Verification of a Reconfigurable Microprocessor.
FPL 2000: 781-784 |
| 1999 |
|---|
| 4 | | Sergej Sawitzki,
Rainer G. Spallek:
A Concept for an Evaluation Framework for Reconfigurable Systems.
FPL 1999: 475-480 |
| 3 | | Sergej Sawitzki:
Gestaltung und Simulation hardware-rekonfigurierbarer Rechnersysteme.
GI Jahrestagung 1999: 239-246 |
| 2 | | Steffen Köhler,
Sergej Sawitzki,
Achim Gratz,
Rainer G. Spallek:
Digital Signal Processing with General Purpose Microprocessors, DSP and Rcinfigurable Logic.
IPPS/SPDP Workshops 1999: 706-708 |
| 1998 |
|---|
| 1 | EE | Sergej Sawitzki,
Achim Gratz,
Rainer G. Spallek:
Increasing Microprocessor Performance with Tightly-Coupled Reconfigurable Logic Arrays.
FPL 1998: 411-415 |
