| 2001 |
|---|
| 4 | EE | Tsukasa Yamauchi,
Shogo Nakaya,
Takeshi Inuo,
Nobuki Kajihara:
Arithmetic Operation Oriented Reconfigurable Chip: RHW.
FPL 2001: 618-622 |
| 2000 |
|---|
| 3 | EE | Tsukasa Yamauchi,
Shogo Nakaya,
Takeshi Inuo,
Nobuki Kajihara:
Mapping Algorithms for a Multi-Bit Data Path Processing Reconfigurable Chip RHW.
FCCM 2000: 281-282 |
| 1998 |
|---|
| 2 | | Hidenori Sakanashi,
Mehrdad Salami,
Masaya Iwata,
Shogo Nakaya,
Tsukasa Yamauchi,
Takeshi Inuo,
Nobuki Kajihara,
Tetsuya Higuchi:
Evolvable Hardware Chip for High Precision Printer Image Compression.
AAAI/IAAI 1998: 486-491 |
| 1996 |
|---|
| 1 | | Tsukasa Yamauchi,
Shogo Nakaya,
Nobuki Kajihara:
SOP: An Adaptive Massively Parallel Computer and its Control-Data-Flow Based Compiling Method.
Parcella 1996: 128-136 |
