| 2009 |
|---|
| 19 | EE | Juan Carlos Moctezuma Eugenio,
Miguel Arias-Estrada:
Hardware/Software FPGA Architecture for Robotics Applications.
ARC 2009: 27-38 |
| 2008 |
|---|
| 18 | EE | Cesar Torres-Huitzil,
Bernard Girau,
Miguel Arias-Estrada:
Biologically-Inspired Digital Architecture for a Cortical Model of Orientation Selectivity.
ICANN (2) 2008: 188-197 |
| 17 | EE | Rafael Lemuz-López,
Miguel Arias-Estrada:
Ranking Corner Points by the Angular Difference between Dominant Edges.
ICVS 2008: 323-332 |
| 2007 |
|---|
| 16 | EE | Griselda Saldaña,
Miguel Arias-Estrada:
Compact FPGA-based systolic array architecture suitable for vision systems.
ITNG 2007: 1008-1013 |
| 2006 |
|---|
| 15 | EE | Alicia Morales-Reyes,
Miguel Arias-Estrada:
Stereo Analysis Extension Based on BRDF Reciprocity.
CONIELECOMP 2006: 53 |
| 14 | EE | Rafael Lemuz-López,
Miguel Arias-Estrada:
Iterative Closest SIFT Formulation for Robust Feature Matching.
ISVC (2) 2006: 502-513 |
| 13 | EE | Rafael Lemuz-López,
Miguel Arias-Estrada:
A Domain Reduction Algorithm for Incremental Projective Reconstruction.
ISVC (2) 2006: 564-575 |
| 2005 |
|---|
| 12 | EE | Gerardo Sosa-Ramirez,
Miguel Arias-Estrada:
3D Recovery with Free Hand Camera Motion.
ENC 2005: 145-151 |
| 11 | EE | Liz Castillo-Jimenez,
Miguel Arias-Estrada:
Super-resolution with integrated radial distortion correction.
ENC 2005: 165-173 |
| 2004 |
|---|
| 10 | EE | Cesar Torres-Huitzil,
Miguel Arias-Estrada:
Real-time image processing with a compact FPGA-based systolic architecture.
Real-Time Imaging 10(3): 177-187 (2004) |
| 2003 |
|---|
| 9 | EE | Cesar Torres-Huitzil,
Miguel Arias-Estrada:
Configurable Hardware Architecture for Real-Time Window-Based Image Processing.
FPL 2003: 1008-1011 |
| 8 | EE | Juan M. Xicotencatl,
Miguel Arias-Estrada:
FPGA Based High Density Spiking Neural Network Array.
FPL 2003: 1053-1056 |
| 7 | EE | Selene Maya-Rueda,
Miguel Arias-Estrada:
FPGA Processor for Real-Time Optical Flow Computation.
FPL 2003: 1103-1106 |
| 2002 |
|---|
| 6 | EE | Miguel Arias-Estrada,
Eduardo Rodríguez-Palacios:
An FPGA Co-processor for Real-Time Visual Tracking.
FPL 2002: 710-719 |
| 2001 |
|---|
| 5 | EE | Miguel Arias-Estrada,
Juan M. Xicotencatl:
Multiple Stereo Matching Using an Extended Architecture.
FPL 2001: 203-212 |
| 2000 |
|---|
| 4 | EE | Cesar Torres-Huitzil,
Miguel Arias-Estrada:
An FPGA Architecture for High Speed Edge and Corner Detection.
CAMP 2000: 112-116 |
| 3 | EE | Selene Maya,
Rocio Reynoso,
César Torres,
Miguel Arias-Estrada:
Compact Spiking Neural Network Implementation in FPGA.
FPL 2000: 270-276 |
| 2 | EE | J. J. Vega,
M. R. Reynoso,
Miguel Arias-Estrada,
Leopoldo Altamirano Robles:
Bragg Curve Identification Using a Neural Network.
IJCNN (4) 2000: 379-382 |
| 1999 |
|---|
| 1 | EE | A. Lecerf,
F. Vachon,
D. Ouellet,
Miguel Arias-Estrada:
FPGA Based Computer Vision Camera.
FPGA 1999: 248 |
