| 2006 |
|---|
| 13 | EE | Oswaldo Cadenas,
Graham M. Megson:
Verification and FPGA Circuits of a Block-2 Fast Path-Based Predictor.
FPL 2006: 1-6 |
| 2005 |
|---|
| 12 | EE | Oswaldo Cadenas,
Graham M. Megson,
Daniel Jones:
Implementation of a block based neural branch predictor.
DSD 2005: 235-238 |
| 11 | | Oswaldo Cadenas,
Graham M. Megson,
Daniel Jones:
FPGA Organization for the Fast Path-Based Neural Branch Predictor.
FPT 2005: 251-258 |
| 10 | EE | Oswaldo Cadenas,
Graham M. Megson,
Daniel Jones:
A New Organization for a Perceptron-Based Branch Predictor and Its FPGA Implementation.
ISVLSI 2005: 305-306 |
| 2004 |
|---|
| 9 | | Oswaldo Cadenas,
Graham M. Megson:
A FPGA pipelined backward adaptive scalar quantizer.
Circuits, Signals, and Systems 2004: 410-415 |
| 8 | EE | Oswaldo Cadenas,
Graham M. Megson:
A clocking technique for FPGA pipelined designs.
Journal of Systems Architecture 50(11): 687-696 (2004) |
| 2003 |
|---|
| 7 | | Oswaldo Cadenas,
Graham M. Megson,
Toomas P. Plaks:
FPGA Circuits for a Monte-Carlo Based Matrix Inversion Architecture.
Engineering of Reconfigurable Systems and Algorithms 2003: 201-207 |
| 6 | EE | Oswaldo Cadenas,
Graham M. Megson:
Pullpipelining: A technique for systolic pipelined circuits.
IWSOC 2003: 205-210 |
| 2002 |
|---|
| 5 | EE | Oswaldo Cadenas,
Graham M. Megson:
Improving mW/MHz Ratio in FPGAs Pipelined Designs.
DSD 2002: 276-282 |
| 4 | EE | Oswaldo Cadenas,
Graham M. Megson:
A Clocking Technique with Power Savings in Virtex-Based Pipelined Designs.
FPL 2002: 322-331 |
| 2001 |
|---|
| 3 | EE | Oswaldo Cadenas,
Graham M. Megson:
Pipelining Considerations for an FPGA Case.
DSD 2001: 276-285 |
| 2 | EE | Oswaldo Cadenas,
Graham M. Megson:
A n-Bit Reconfigurable Scalar Quantiser.
FPL 2001: 420-429 |
| 1999 |
|---|
| 1 | | Toomas P. Plaks,
Oswaldo Cadenas,
Graham M. Megson:
Experiences Using Reconfigurable FPGAs in Implementing Monte-Carlo Methods.
PDPTA 1999: 1131-1137 |
