2009 | ||
---|---|---|
65 | EE | Clémentin Tayou Djamégni, Patrice Quinton, Sanjay V. Rajopadhye, Tanguy Risset, Maurice Tchuente: A reindexing based approach towards mapping of DAG with affine schedules onto parallel embedded systems. J. Parallel Distrib. Comput. 69(1): 1-11 (2009) |
2008 | ||
64 | EE | Nissa Osheim, Michelle Mills Strout, Dave Rostron, Sanjay V. Rajopadhye: Smashing: Folding Space to Tile through Time. LCPC 2008: 80-93 |
63 | EE | Sanjay V. Rajopadhye, Gautam Gupta, Lakshminarayanan Renganarayanan: A domain specific interconnect for reconfigurable computing. LCTES 2008: 79-88 |
62 | EE | Lakshminarayanan Renganarayanan, Sanjay V. Rajopadhye: Positivity, posynomials and tile size selection. SC 2008: 55 |
2007 | ||
61 | EE | Gautam Gupta, DaeGon Kim, Sanjay V. Rajopadhye: Scheduling in the Z-Polyhedral Model. IPDPS 2007: 1-10 |
60 | EE | Lakshminarayanan Renganarayanan, Manjukumar Harthikote-Matha, Rinku Dewri, Sanjay V. Rajopadhye: Towards Optimal Multi-level Tiling for Stencil Computations. IPDPS 2007: 1-10 |
59 | EE | Lakshminarayanan Renganarayanan, DaeGon Kim, Sanjay V. Rajopadhye, Michelle Mills Strout: Parameterized tiled loops for free. PLDI 2007: 405-414 |
58 | EE | Gautam Gupta, Sanjay V. Rajopadhye: The Z-polyhedral model. PPOPP 2007: 237-248 |
57 | EE | DaeGon Kim, Lakshminarayanan Renganarayanan, Dave Rostron, Sanjay V. Rajopadhye, Michelle Mills Strout: Multi-level tiling: M for the price of one. SC 2007: 51 |
2006 | ||
56 | EE | DaeGon Kim, Sanjay V. Rajopadhye: An Improved Systolic Architecture for LU Decomposition. ASAP 2006: 231-238 |
55 | EE | DaeGon Kim, Gautam Gupta, Sanjay V. Rajopadhye: On Control Signals for Multi-Dimensional Time. LCPC 2006: 141-155 |
54 | EE | Gautam Gupta, Sanjay V. Rajopadhye: Simplifying reductions. POPL 2006: 30-41 |
2005 | ||
53 | Sanjay V. Rajopadhye, Kolin Paul: A 1.5-D Architecture for Back-Propagation Training. ERSA 2005: 112-118 | |
52 | EE | Lakshminarayanan Renganarayanan, U. Ramakrishna, Sanjay V. Rajopadhye: Combined ILP and Register Tiling: Analytical Model and Optimization Framework. LCPC 2005: 244-258 |
2004 | ||
51 | EE | Lakshminarayanan Renganarayanan, Sanjay V. Rajopadhye: A Geometric Programming Framework for Optimal Multi-Level Tiling. SC 2004: 18 |
2003 | ||
50 | EE | Lakshminarayanan Renganarayanan, Sanjay V. Rajopadhye: Switched Memory Architectures-Moving Beyond Systolic Arrays. ASAP 2003: 28-39 |
49 | EE | Rumen Andonov, Stephan Balev, Sanjay V. Rajopadhye, Nicola Yanev: Optimal Semi-Oblique Tiling. IEEE Trans. Parallel Distrib. Syst. 14(9): 944-960 (2003) |
2002 | ||
48 | EE | Sanjay V. Rajopadhye, Steven Derrien: Energy/Power Estimation of Regular Processor Arrays. ISSS 2002: 50-55 |
47 | EE | Gautam Gupta, Sanjay V. Rajopadhye, Patrice Quinton: Scheduling reductions on realistic machines. SPAA 2002: 117-126 |
46 | Sanjay V. Rajopadhye: Dependence Analysis and Parallelizing Transformations. The Compiler Design Handbook 2002: 329-372 | |
2001 | ||
45 | EE | Steven Derrien, Sanjay V. Rajopadhye: Loop Tiling for Reconfigurable Accelerators. FPL 2001: 398-408 |
44 | EE | Manju Manjunathaiah, Graham M. Megson, Sanjay V. Rajopadhye, Tanguy Risset: Uniformization of Affine Dependance Programs for Parallel Embedded System Design. ICPP 2001: 205-213 |
43 | David Cachera, Patrice Quinton, Sanjay V. Rajopadhye, Tanguy Risset: Proving Properties of Multidimensional Recurrences with Application to Regular Parallel Algorithms. IPDPS 2001: 148 | |
42 | Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay: Combined instruction and loop parallelism in array synthesis for FPGAs. ISSS 2001: 165-170 | |
41 | EE | Rumen Andonov, Stephan Balev, Sanjay V. Rajopadhye, Nicola Yanev: Optimal semi-oblique tiling. SPAA 2001: 153-162 |
2000 | ||
40 | EE | Scott Bowden, Doran Wilde, Sanjay V. Rajopadhye: Quadratic Control Signals in Linear Systolic Arrays. ASAP 2000: 268-275 |
39 | EE | Steven Derrien, Sanjay V. Rajopadhye: FCCMS and the Memory Wall. FCCM 2000: 329-330 |
38 | EE | Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay: Optimal Partitioning for FPGA Based Regular Array Implementations. PARELEC 2000: 155-159 |
37 | EE | Fabien Quilleré, Sanjay V. Rajopadhye: Optimizing memory usage in the polyhedral model. ACM Trans. Program. Lang. Syst. 22(5): 773-815 (2000) |
36 | Fabien Quilleré, Sanjay V. Rajopadhye, Doran Wilde: Generation of Efficient Nested Loops from Polyhedra. International Journal of Parallel Programming 28(5): 469-498 (2000) | |
35 | Clémentin Tayou Djamégni, Patrice Quinton, Sanjay V. Rajopadhye, Tanguy Risset: Derivation of systolic algorithms for the algebraic path problem by recurrence transformations. Parallel Computing 26(11): 1429-1445 (2000) | |
1999 | ||
34 | EE | Sanjay V. Rajopadhye, Claude Tadonki, Tanguy Risset: The Algebraic Path Problem Revisited. Euro-Par 1999: 698-707 |
1998 | ||
33 | EE | Rumen Andonov, Sanjay V. Rajopadhye, Nicola Yanev: Optimal Orthogonal Tiling. Euro-Par 1998: 480-490 |
32 | EE | Stephan Balev, Patrice Quinton, Sanjay V. Rajopadhye, Tanguy Risset: Linear Programming Models for Scheduling Systems of Affine Recurrence Equations - A Comparative Study. SPAA 1998: 250-258 |
1997 | ||
31 | Patrick M. Lenders, Sanjay V. Rajopadhye: Multirate VLSI Arrays and Their Synthesis. IEEE Trans. Computers 46(5): 515-529 (1997) | |
30 | EE | Rumen Andonov, Sanjay V. Rajopadhye: Knapsack on VLSI: from Algorithm to Optimal Circuit. IEEE Trans. Parallel Distrib. Syst. 8(6): 545-561 (1997) |
29 | Rumen Andonov, Sanjay V. Rajopadhye: Optimal Orthogonal Tiling of 2-D Iterations. J. Parallel Distrib. Comput. 45(2): 159-165 (1997) | |
28 | Patrice Quinton, Sanjay V. Rajopadhye, Tanguy Risset: On Manipulating Z-Polyhedra Using a Canonical Representation. Parallel Processing Letters 7(2): 181-194 (1997) | |
27 | Doran Wilde, Sanjay V. Rajopadhye: Memory Reuse Analysis in the Polyhedral Model. Parallel Processing Letters 7(2): 203-215 (1997) | |
1996 | ||
26 | EE | Patrice Quinton, Sanjay V. Rajopadhye, Tanguy Risset: Extension Of The Alpha Language To Recurrences On Sparse Periodic Domains. ASAP 1996: 391-401 |
25 | Doran Wilde, Sanjay V. Rajopadhye: Memory Reuse Analysis in the Polyhedral Model. Euro-Par, Vol. I 1996: 389-397 | |
24 | Florent de Dinechin, Doran Wilde, Sanjay V. Rajopadhye, Rumen Andonov: A Regular VLSI Array for an Irregular Algorithm. IRREGULAR 1996: 195-200 | |
23 | EE | Virginia Mary Lo, Sanjay V. Rajopadhye, Jan Arne Telle, Xiaoxiong Zhong: Parallel Divide and Conquer on Meshes. IEEE Trans. Parallel Distrib. Syst. 7(10): 1049-1058 (1996) |
1995 | ||
22 | EE | Doran Wilde, Sanjay V. Rajopadhye: The naive execution of affine recurrence equations. ASAP 1995: 1-12 |
21 | EE | Patrick M. Lenders, Sanjay V. Rajopadhye: Synthesis of Multirate VLSI Arrays. ASAP 1995: 310-321 |
20 | Patrice Quinton, Sanjay V. Rajopadhye, Doran Wilde: Deriving Imperative Code from Functional Programs. FPCA 1995: 36-44 | |
19 | EE | Patrice Quinton, Sanjay V. Rajopadhye, Doran Wilde: On deriving data parallel code from a functional program. IPPS 1995: 766- |
18 | Rumen Andonov, Patrice Quinton, Sanjay V. Rajopadhye, Doran Wilde: A Shift Registered-Based Systolic Array for the Unbounded Knapsack Problem. Parallel Processing Letters 5: 251-262 (1995) | |
1994 | ||
17 | Rumen Andonov, Sanjay V. Rajopadhye: Optimal Tile Sizing. CONPAR 1994: 701-712 | |
16 | Rumen Andonov, Patrice Quinton, Sanjay V. Rajopadhye, Doran Wilde: Pure Systolic Array for a Class of Dynamic Dependency Recurrences. Parcella 1994: 207-214 | |
1993 | ||
15 | Sanjay V. Rajopadhye, Manjunath Muddarangegowda: Parallel Assignment, Reduction and Communication for Data Parallel Programming. PPSC 1993: 850-853 | |
14 | Sanjay V. Rajopadhye: Analysis of Affine Communication Specifications. SPDP 1993: 530-537 | |
1992 | ||
13 | Björn Lisper, Sanjay V. Rajopadhye: Reasoning about Permutations in Regular Arrays. Designing Correct Circuits 1992: 139-157 | |
12 | Xiaoxiong Zhong, Sanjay V. Rajopadhye, Virginia Mary Lo: Parallel Implementation of Divide-and-Conquer Algorithms on Binary de Bruijn Networks. IPPS 1992: 103-107 | |
11 | EE | Xiaoxiong Zhong, Sanjay V. Rajopadhye: Quasi-Linear allocation functions for efficient array design. VLSI Signal Processing 4(2-3): 97-110 (1992) |
10 | EE | Xiaoxiong Zhong, Sanjay V. Rajopadhye, Ivan Wong: Systematic generation of linear allocation functions in systolic array design. VLSI Signal Processing 4(4): 279-293 (1992) |
1991 | ||
9 | Sanjay V. Rajopadhye: An improved systolic algorithm for the algebraic path problem. Algorithms and Parallel VLSI Architectures 1991: 187-198 | |
8 | Xiaoxiong Zhong, Sanjay V. Rajopadhye: Deriving Fully Efficient Systolic Arrays by Quasi-Linear Allocation Functions. PARLE (1) 1991: 219-236 | |
1990 | ||
7 | Virginia Mary Lo, Sanjay V. Rajopadhye, Samik Gupta, David Keldsen, Moataz A. Mohamed, Jan Arne Telle: OREGAMI: Software Tools for Mapping Parallel Computations to Parallel Architectures. ICPP (2) 1990: 88-92 | |
6 | Virginia Mary Lo, Sanjay V. Rajopadhye, Samik Gupta, David Keldsen, Moataz A. Mohamed, Jan Arne Telle: Mapping Divide-and-Conquer Algorithms to Parallel Architectures. ICPP (3) 1990: 128-135 | |
5 | Sanjay V. Rajopadhye, Richard Fujimoto: Synthesizing systolic arrays from recurrence equations. Parallel Computing 14(2): 163-189 (1990) | |
1989 | ||
4 | Sanjay V. Rajopadhye: Synthesizing Systolic Arrays with Control Signals from Recurrence Equations. Distributed Computing 3(2): 88-105 (1989) | |
1987 | ||
3 | Sanjay V. Rajopadhye, Richard Fujimoto: Systolic Array Synthesis by Static Analysis of Program Dependencies. PARLE (1) 1987: 295-310 | |
1986 | ||
2 | Sanjay V. Rajopadhye, S. Purushothaman, Richard Fujimoto: On Synthesizing Systolic Arrays from Recurrence Equations with Linear Dependencies. FSTTCS 1986: 488-503 | |
1 | Sanjay V. Rajopadhye, Prakash Panangaden: Verification of Systolic Arrays: A Stream Function Approach. ICPP 1986: 773-775 |