| 2005 |
|---|
| 13 | EE | Andreas Dandalis,
Viktor K. Prasanna:
Configuration compression for FPGA-based embedded systems.
IEEE Trans. VLSI Syst. 13(12): 1394-1398 (2005) |
| 2004 |
|---|
| 12 | EE | Andreas Dandalis,
Viktor K. Prasanna:
An adaptive cryptographic engine for internet protocol security architectures.
ACM Trans. Design Autom. Electr. Syst. 9(3): 333-353 (2004) |
| 2002 |
|---|
| 11 | EE | Andreas Dandalis,
Viktor K. Prasanna:
Run-time performance optimization of an FPGA-based deduction engine for SAT solvers.
ACM Trans. Design Autom. Electr. Syst. 7(4): 547-562 (2002) |
| 2001 |
|---|
| 10 | EE | Andreas Dandalis,
Viktor K. Prasanna:
Configuration compression for FPGA-based embedded systems.
FPGA 2001: 173-182 |
| 9 | EE | Andreas Dandalis,
Viktor K. Prasanna,
Bharani Thiruvengadam:
Run-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT Solvers.
FPL 2001: 315-325 |
| 2000 |
|---|
| 8 | EE | Andreas Dandalis,
Viktor K. Prasanna,
José D. P. Rolim:
A Comparative Study of Performance of AES Final Candidates Using FPGAs.
CHES 2000: 125-140 |
| 7 | EE | Andreas Dandalis,
Viktor K. Prasanna,
José D. P. Rolim:
An Adaptive Cryptographic Engine for IPSec Architectures.
FCCM 2000: 132-144 |
| 6 | EE | Sameer Wadhwa,
Andreas Dandalis:
Efficient Self-Reconfigurable Implementations Using On-chip Memory.
FPL 2000: 443-448 |
| 5 | EE | M. Redekopp,
Andreas Dandalis:
A Parallel Pipelined SAT Solver for FPGAs.
FPL 2000: 462-468 |
| 1999 |
|---|
| 4 | | Andreas Dandalis,
Alessandro Mei,
Viktor K. Prasanna:
Domain Specific Mapping for Solving Graph Problems on Reconfigurable Devices.
IPPS/SPDP Workshops 1999: 652-660 |
| 1998 |
|---|
| 3 | EE | Andreas Dandalis,
Viktor K. Prasanna:
Mapping Homogeneous Computations onto Dynamically Configurable Coarse-Grained Architectures.
FCCM 1998: 314- |
| 2 | EE | Andreas Dandalis,
Viktor K. Prasanna:
Space-efficient Mapping of 2D-DCT onto Dynamically Configurable Coarse-Grained Architectures.
FPL 1998: 471-475 |
| 1997 |
|---|
| 1 | | Andreas Dandalis,
Viktor K. Prasanna:
Fast parallel implementation of DFT using configurable devices.
FPL 1997: 314-323 |
