Máire McLoone

2007
16	EE	Máire McLoone, Matthew J. B. Robshaw: Public Key Cryptography and RFID Tags. CT-RSA 2007: 372-384
15	EE	Máire McLoone, Matthew J. B. Robshaw: New Architectures for Low-Cost Public Key Cryptography on RFID Tags. ISCAS 2007: 1827-1830
14	EE	Nicolas Sklavos, Máire McLoone, Xinmiao Zhang: MONET Special Issue on Next Generation Hardware Architectures for Secure Mobile Computing. MONET 12(4): 229-230 (2007)
13	EE	Máire McLoone, Ciaran McIvor: High-speed & Low Area Hardware Architectures of the Whirlpool Hash Function. VLSI Signal Processing 47(1): 47-57 (2007)
2006
12	EE	Neil Smyth, Máire McLoone, John V. McCanny: An Adaptable And Scalable Asymmetric Cryptographic Processor. ASAP 2006: 341-346
11	EE	Ghazanfar Ali Safdar, Clare McGrath, Máire McLoone: Limitations of existing wireless networks authentication and key management techniques for MANETs. ISCN 2006: 101-105
2005
10	EE	P. Moore, Máire McLoone, Sakir Sezer: Reconfigurable Instruction Interface Architecture for Private-Key Cryptography on the Altera Nios-II Processor. AICT/SAPIR/ELETE 2005: 296-299
9		Ciaran McIvor, Máire McLoone, John V. McCanny: High-Radix Systolic Modular Multiplication on Reconfigurable Hardware. FPT 2005: 13-18
8		Máire McLoone, Ciaran McIvor, Aidan Savage: High-Speed Hardware Architectures of the Whirlpool Hash Function. FPT 2005: 147-162
2004
7	EE	Ciaran McIvor, Máire McLoone, John V. McCanny: FPGA Montgomery Multiplier Architectures - A Comparison. FCCM 2004: 279-282
6	EE	Ciaran McIvor, Máire McLoone, John V. McCanny: FPGA Montgomery modular multiplication architectures suitable for ECCs over GF(p). ISCAS (3) 2004: 509-512
2003
5	EE	Máire McLoone, John V. McCanny: Very High Speed 17 Gbps SHACAL Encryption Architecture. FPL 2003: 111-120
4	EE	Ciaran McIvor, Máire McLoone, John V. McCanny: A high-speed, low latency RSA decryption silicon core. ISCAS (4) 2003: 133-136
3	EE	Máire McLoone, John V. McCanny: Rijndael FPGA Implementations Utilising Look-Up Tables. VLSI Signal Processing 34(3): 261-275 (2003)
2001
2	EE	Máire McLoone, John V. McCanny: High Performance Single-Chip FPGA Rijndael Algorithm Implementations. CHES 2001: 65-76
1	EE	Máire McLoone, John V. McCanny: Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm. FPL 2001: 152-161

Coauthor Index

1	John V. McCanny	[1] [2] [3] [4] [5] [6] [7] [9] [12]
2	Clare McGrath	[11]
3	Ciaran McIvor	[4] [6] [7] [8] [9] [13]
4	P. Moore	[10]
5	Matthew J. B. Robshaw	[15] [16]
6	Ghazanfar Ali Safdar	[11]
7	Aidan Savage	[8]
8	Sakir Sezer	[10]
9	Nicolas Sklavos	[14]
10	Neil Smyth	[12]
11	Xinmiao Zhang	[14]

Colors in the list of coauthors