N. Bhavanishankar
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1996
1
EE
N. Ranganathan
,
Narayanan Vijaykrishnan
, N. Bhavanishankar: A VLSI array architecture with dynamic frequency clocking.
ICCD 1996
: 137-140
Coauthor
Index
1
N. Ranganathan
(Nagarajan Ranganathan)
[
1
]
2
Narayanan Vijaykrishnan
(Vijaykrishnan Narayanan)
[
1
]
Copyright ©
Sun May 17 03:24:02 2009 by
Michael Ley
(
ley@uni-trier.de
)
