M. Varanasi

List of publications from the DBLP Bibliography Server - FAQ

1993

3 Mario Kovac, N. Ranganathan, M. Varanasi: SIGMA: A VLSI Chip for Galois Field GF(2^m) Based Multiplication and Division. VLSI Design 1993: 25-30

2 EE Mario Kovac, N. Ranganathan, M. Varanasi: SIGMA: a VLSI systolic array implementation of a Galois field GF(2 ^m) based multiplication and division algorithm. IEEE Trans. VLSI Syst. 1(1): 22-30 (1993)

1992

1 Mario Kovac, N. Ranganathan, M. Varanasi: A Systolic Algorithm and Architecture for Galois Field Arithmetic. IPPS 1992: 283-288

1993
3		Mario Kovac, N. Ranganathan, M. Varanasi: SIGMA: A VLSI Chip for Galois Field GF(2^m) Based Multiplication and Division. VLSI Design 1993: 25-30
2	EE	Mario Kovac, N. Ranganathan, M. Varanasi: SIGMA: a VLSI systolic array implementation of a Galois field GF(2 ^m) based multiplication and division algorithm. IEEE Trans. VLSI Syst. 1(1): 22-30 (1993)
1992
1		Mario Kovac, N. Ranganathan, M. Varanasi: A Systolic Algorithm and Architecture for Galois Field Arithmetic. IPPS 1992: 283-288

Coauthor Index

1 Mario Kovac [1] [2] [3]

2 N. Ranganathan (Nagarajan Ranganathan) [1] [2] [3]

1	Mario Kovac	[1] [2] [3]
2	N. Ranganathan (Nagarajan Ranganathan)	[1] [2] [3]