ASAP 2002:
San Jose,
CA,
USA
13th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2002), 17-19 July 2002, San Jose, CA, USA.
IEEE Computer Society 2002, ISBN 0-7695-1712-9 BibTeX
@proceedings{DBLP:conf/asap/2002,
title = {13th IEEE International Conference on Application-Specific Systems,
Architectures, and Processors (ASAP 2002), 17-19 July 2002, San
Jose, CA, USA},
publisher = {IEEE Computer Society},
year = {2002},
isbn = {0-7695-1712-9},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Keynote Presentation
Design Methodologies
Low Power Design
Computer Arithmetic I
Memory Organization
- James Irwin, David May, Henk L. Muller, Dan Page:
Predictable Instruction Caching for Media Processors.
141-150
Electronic Edition (link) BibTeX
- Afzal Hossain, Daniel J. Pease, James S. Burns, Nasima Parveen:
A Mathematical Model of Trace Cache.
151-162
Electronic Edition (link) BibTeX
- Jeffrey T. Draper, Jeff Sondeen, Sumit D. Mediratta, Ihn Kim:
Implementation of a 32-bit RISC Processor for the Data-Intensive Architecture Processing-In-Memory Chip.
163-172
Electronic Edition (link) BibTeX
- Woo-Chan Park, Kil-Whan Lee, Il-San Kim, Tack-Don Han, Sung-Bong Yang:
A Mid-Texturing Pixel Rasterization Pipeline Architecture for 3D Rendering Processors.
173-
Electronic Edition (link) BibTeX
Computer Arithmetic II
Media Processors
- Byeong Kil Lee, Lizy Kurian John:
Implications of Programmable General Purpose Processors for Compression/Encryption Applications.
233-242
Electronic Edition (link) BibTeX
- Chris Y. Chung, Ravi Managuli, Yongmin Kim:
Design and Evaluation of a Multimedia Computing Architecture Based on a 3D Graphics Pipeline.
243-252
Electronic Edition (link) BibTeX
- Ruby B. Lee, A. Murat Fiskiran, Zhijie Shi, Xiao Yang:
Refining Instruction Set Architecture for High-Performance Multimedia Processing in Constrained Environments.
253-264
Electronic Edition (link) BibTeX
- Julio Villalba, Gerardo Bandera, Mario A. González, Javier Hormigo, Emilio L. Zapata:
Polynomial Evaluation on Multimedia Processors.
265-
Electronic Edition (link) BibTeX
Cryptography
VLSI Architectures
- E. I. Chester, John N. Coleman:
Matrix Engine for Signal Processing Applications Using the Logarithmic Number System.
315-324
Electronic Edition (link) BibTeX
- K. Sitaraman, N. Ranganathan, Abdel Ejnioui:
A VLSI Architecture for Object Recognition Using Tree Matching.
325-334
Electronic Edition (link) BibTeX
- Steven M. Currie, Paul R. Schumacher, Barry K. Gilbert, Earl E. Swartzlander Jr., Barbara A. Randall:
Implementation of a Single Chip, Pipelined, Complex, One-Dimensional Fast FourierTransform in 0.25 mu m BulkCMOS.
335-343
Electronic Edition (link) BibTeX
- Roger D. Chamberlain, Mark A. Franklin, Praveen Krishnamurthy:
Optical Network Reconfiguration for Signal Processing Applications.
344-
Electronic Edition (link) BibTeX
Application-Specific System Design
Copyright © Sat May 16 22:58:34 2009
by Michael Ley (ley@uni-trier.de)
