| 1998 |
|---|
| 13 | | Raghu Sastry,
N. Ranganathan:
A VLSI Architecture for Approximate Tree Matching.
IEEE Trans. Computers 47(3): 346-352 (1998) |
| 12 | EE | N. Ranganathan,
Raghu Sastry,
R. Venkatesan:
SMAC: A VLSI Architecture for Scene Matching.
Real-Time Imaging 4(3): 171-180 (1998) |
| 1996 |
|---|
| 11 | | Albert Mu,
Jeff Larson,
Raghu Sastry,
Thomas Wicki,
Winfried W. Wilcke:
A 9.6 GigaByte/s Throughput Plesiochronous Routing Chip.
COMPCON 1996: 261-266 |
| 1995 |
|---|
| 10 | | Raghu Sastry,
N. Ranganathan:
A VLSI Architecture for Computer the Tree-to-Tree Distance.
HPCA 1995: 330-339 |
| 9 | EE | Raghu Sastry,
N. Ranganathan,
Klinton Remedios:
CASM: A VLSI Chip for Approximate String Matching.
IEEE Trans. Pattern Anal. Mach. Intell. 17(8): 824-830 (1995) |
| 8 | EE | Raghu Sastry,
N. Ranganathan,
Ramesh Jain:
VLSI Architectures for High-Speed Range Estimation.
IEEE Trans. Pattern Anal. Mach. Intell. 17(9): 894-899 (1995) |
| 7 | | Raghu Sastry,
N. Ranganathan:
PMAC: A Polygon Matching Chip.
IJPRAI 9(2): 367-385 (1995) |
| 1994 |
|---|
| 6 | | N. Ranganathan,
Raghu Sastry:
VLSI Architectures for Pattern Matching.
IJPRAI 8(4): 815-843 (1994) |
| 1993 |
|---|
| 5 | | N. Ranganathan,
Raghu Sastry,
R. Venkatesan,
Joseph W. Yoder,
David C. Keezer:
SMAC: A Scene Matching Chip.
ICCD 1993: 184-187 |
| 4 | | Raghu Sastry,
N. Ranganathan:
A Systolic Array for Approximate String Matching.
ICCD 1993: 402-405 |
| 3 | | Raghu Sastry,
N. Ranganathan,
Ramesh Jain:
VLSI Architectures for Depth Estimation Using Intensity Gradient Analysis.
IPPS 1993: 700-704 |
| 2 | | Raghu Sastry,
N. Ranganathan,
Horst Bunke:
Hardware Algorithms for Polygon Matching.
VLSI Design 1993: 41-44 |
| 1 | EE | Raghu Sastry,
N. Ranganathan,
Horst Bunke:
VLSI architectures for polygon recognition.
IEEE Trans. VLSI Syst. 1(4): 398-407 (1993) |
