| 2006 |
|---|
| 6 | EE | Sangjin Hong,
Shu-Shin Chin,
Petar M. Djuric,
Miodrag Bolic:
Design and Implementation of Flexible Resampling Mechanism for High-Speed Parallel Particle Filters.
VLSI Signal Processing 44(1-2): 47-62 (2006) |
| 2005 |
|---|
| 5 | EE | Sangjin Hong,
Shu-Shin Chin:
Domain Specific Reconfigurable Processing Core Architecture for Digital Filtering Applications.
VLSI Signal Processing 40(2): 239-259 (2005) |
| 2004 |
|---|
| 4 | | Sangjin Hong,
Shu-Shin Chin,
Magesh Sadasivam:
Glitching power reduction through supply voltage adaptation mechanism for low power array structure design.
ISCAS (2) 2004: 733-736 |
| 3 | EE | Shu-Shin Chin,
Sangjin Hong,
Suhwan Kim:
Usage of Application-Specific Switching Activity for Energy Minimization of Arithmetic Units.
ISVLSI 2004: 158-166 |
| 2 | EE | Sangjin Hong,
Shu-Shin Chin:
Incorporating Power Reduction Mechanism in Arithmetic Core Design.
ISVLSI 2004: 249-250 |
| 1 | EE | Sangjin Hong,
Shu-Shin Chin,
Suhwan Kim,
Wei Hwang:
Power Reduction Technique in Coefficient Multiplications Through Multiplier Characterization.
VLSI Signal Processing 38(2): 101-113 (2004) |
