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Shu-Shin Chin

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2006
6EESangjin Hong, Shu-Shin Chin, Petar M. Djuric, Miodrag Bolic: Design and Implementation of Flexible Resampling Mechanism for High-Speed Parallel Particle Filters. VLSI Signal Processing 44(1-2): 47-62 (2006)
2005
5EESangjin Hong, Shu-Shin Chin: Domain Specific Reconfigurable Processing Core Architecture for Digital Filtering Applications. VLSI Signal Processing 40(2): 239-259 (2005)
2004
4 Sangjin Hong, Shu-Shin Chin, Magesh Sadasivam: Glitching power reduction through supply voltage adaptation mechanism for low power array structure design. ISCAS (2) 2004: 733-736
3EEShu-Shin Chin, Sangjin Hong, Suhwan Kim: Usage of Application-Specific Switching Activity for Energy Minimization of Arithmetic Units. ISVLSI 2004: 158-166
2EESangjin Hong, Shu-Shin Chin: Incorporating Power Reduction Mechanism in Arithmetic Core Design. ISVLSI 2004: 249-250
1EESangjin Hong, Shu-Shin Chin, Suhwan Kim, Wei Hwang: Power Reduction Technique in Coefficient Multiplications Through Multiplier Characterization. VLSI Signal Processing 38(2): 101-113 (2004)

Coauthor Index

1Miodrag Bolic [6]
2Petar M. Djuric [6]
3Sangjin Hong [1] [2] [3] [4] [5] [6]
4Wei Hwang [1]
5Suhwan Kim [1] [3]
6Magesh Sadasivam [4]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)