2009 | ||
---|---|---|
42 | EE | Colin J. Ihrig, Gerold Joseph Dhanabalan, Alex K. Jones: A low-power CMOS thyristor based delay element with programmability extensions. ACM Great Lakes Symposium on VLSI 2009: 297-302 |
41 | EE | Swapna R. Dontharaju, Shen Chih Tung, James T. Cain, Leonid Mats, Marlin H. Mickle, Alex K. Jones: A design automation and power estimation flow for RFID systems. ACM Trans. Design Autom. Electr. Syst. 14(1): (2009) |
40 | EE | Gayatri Mehta, Justin Stander, Mustafa Baz, Brady Hunsaker, Alex K. Jones: Interconnect customization for a hardware fabric. ACM Trans. Design Autom. Electr. Syst. 14(1): (2009) |
39 | EE | Shuyi Shao, Alex K. Jones, Rami G. Melhem: Compiler Techniques for Efficient Communications in Circuit Switched Networks for Multiprocessor Systems. IEEE Trans. Parallel Distrib. Syst. 20(3): 331-345 (2009) |
2008 | ||
38 | EE | Ying Yu, Raymond R. Hoare, Alex K. Jones: A CAM-based intrusion detection system for single-packet attack detection. IPDPS 2008: 1-8 |
37 | EE | Shen Chih Tung, Alex K. Jones: Physical layer design automation for RFID systems. IPDPS 2008: 1-8 |
36 | EE | Gayatri Mehta, Colin J. Ihrig, Alex K. Jones: Reducing energy by exploring heterogeneity in a coarse-grain fabric. IPDPS 2008: 1-8 |
35 | EE | Shuyi Shao, Yu Zhang, Alex K. Jones, Rami G. Melhem: Symbolic expression analysis for compiled communication. IPDPS 2008: 1-8 |
34 | EE | Alex K. Jones, Swapna R. Dontharaju, Shen Chih Tung, Leonid Mats, Peter J. Hawrylak, Raymond R. Hoare, James T. Cain, Marlin H. Mickle: Radio frequency identification prototyping. ACM Trans. Design Autom. Electr. Syst. 13(2): (2008) |
33 | EE | Alex K. Jones, Robert Walker: Introduction to the special section on demonstrable software systems and hardware platforms II. ACM Trans. Design Autom. Electr. Syst. 13(3): (2008) |
32 | EE | Raymond R. Hoare, Zhu Ding, Alex K. Jones: A two-stage hardware scheduler combining greedy and optimal scheduling. J. Parallel Distrib. Comput. 68(11): 1437-1451 (2008) |
2007 | ||
31 | EE | Gayatri Mehta, Justin Stander, Mustafa Baz, Brady Hunsaker, Alex K. Jones: Interconnect Customization for a Coarse-grained Reconfigurable Fabric. IPDPS 2007: 1-8 |
30 | EE | Alex K. Jones, Raymond R. Hoare, Joseph St. Onge, Joshua M. Lucas, Shuyi Shao, Rami G. Melhem: Linking Compilation and Visualization for Massively Parallel Programs. IPDPS 2007: 1-8 |
29 | EE | Colin J. Ihrig, Justin Stander, Alex K. Jones: Pipelining Tradeoffs of Massively Parallel SuperCISC Hardware Functions. IPDPS 2007: 1-8 |
28 | EE | Alex K. Jones, Raymond Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle: An automated, FPGA-based reconfigurable, low-power RFID tag. Microprocessors and Microsystems 31(2): 116-134 (2007) |
2006 | ||
27 | EE | Alex K. Jones, Raymond R. Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle: An automated, reconfigurable, low-power RFID tag. DAC 2006: 131-136 |
26 | EE | Alex K. Jones, Raymond R. Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle: A Field Programmable RFID Tag and Associated Design Flow. FCCM 2006: 165-174 |
25 | EE | Raymond R. Hoare, Ivan S. Kourtev, Alex K. Jones: Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM). FCCM 2006: 299-300 |
24 | EE | Gayatri Mehta, Raymond R. Hoare, Justin Stander, Alex K. Jones: A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture. FCCM 2006: 309-310 |
23 | EE | Shuyi Shao, Alex K. Jones, Rami G. Melhem: A compiler-based communication analysis approach for multiprocessor systems. IPDPS 2006 |
22 | EE | Gayatri Mehta, Raymond R. Hoare, Justin Stander, Alex K. Jones: Design space exploration for low-power reconfigurable fabrics. IPDPS 2006 |
21 | EE | Ying Yu, Raymond R. Hoare, Alex K. Jones, Ralph Sprang: A hybrid encoding scheme for efficient single-cycle range matching in content addressable memory. ISCAS 2006 |
20 | EE | Raymond R. Hoare, Zhu Ding, Alex K. Jones: Interconnect routing and scheduling - A near-optimal real-time hardware scheduler for large cardinality crossbar switches. SC 2006: 94 |
19 | EE | Zhu Ding, Raymond R. Hoare, Alex K. Jones, Rami G. Melhem: Interconnect routing and scheduling - Level-wise scheduling algorithm for fat tree interconnection networks. SC 2006: 96 |
18 | EE | Alex K. Jones, Raymond Hoare, Dara Kusic, Gayatri Mehta, Joshua Fazekas, John Foster: Reducing power while increasing performance with supercisc. ACM Trans. Embedded Comput. Syst. 5(3): 658-686 (2006) |
17 | EE | Alex K. Jones, Jiang Zheng, Ahmed Amer: Entropy Based Evaluation of Communication Predictability in Parallel Applications. IEICE Transactions 89-D(2): 469-478 (2006) |
16 | EE | Alex K. Jones, Swapna R. Dontharaju, Shen Chih Tung, Peter J. Hawrylak, Leonid Mats, Raymond R. Hoare, James T. Cain, Marlin H. Mickle: Passive active radio frequency identification tags. IJRFITA 1(1): 52-73 (2006) |
15 | EE | Gayatri Mehta, Justin Stander, Joshua M. Lucas, Raymond R. Hoare, Brady Hunsaker, Alex K. Jones: A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture. J. Low Power Electronics 2(2): 148-164 (2006) |
14 | EE | Joshua M. Lucas, Raymond Hoare, Ivan S. Kourtev, Alex K. Jones: Technology mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM). Microprocessors and Microsystems 30(7): 445-456 (2006) |
2005 | ||
13 | EE | Joshua M. Lucas, Raymond Hoare, Alex K. Jones: Optimizing Technology Mapping for FPGAs Using CAMs. FCCM 2005: 293-294 |
12 | EE | Alex K. Jones, Raymond Hoare, Dara Kusic, Joshua Fazekas, John Foster: An FPGA-based VLIW processor with custom hardware execution. FPGA 2005: 107-117 |
11 | EE | Dara Kusic, Raymond Hoare, Alex K. Jones, Joshua Fazekas, John Foster: Extracting Speedup From C-Code With Poor Instruction-Level Parallelism. IPDPS 2005 |
10 | EE | Zhu Ding, Raymond R. Hoare, Alex K. Jones, Dan Li, Shou-Kuo Shao, Shen-Chien Tung, Jiang Zheng, Rami G. Melhem: Switch Design to Enable Predictive Multiplexed Switching in Multiprocessor Networks. IPDPS 2005 |
9 | EE | Kevin J. Barker, Alan F. Benner, Raymond R. Hoare, Adolfy Hoisie, Alex K. Jones, Darren J. Kerbyson, Dan Li, Rami G. Melhem, Ramakrishnan Rajamony, Eugen Schenfeld, Shuyi Shao, Craig B. Stunkel, Peter Walker: On the Feasibility of Optical Circuit Switching for High Performance Computing Systems. SC 2005: 16 |
8 | EE | Xiaoyong Tang, Tianyi Jiang, Alex K. Jones, Prithviraj Banerjee: Behavioral Synthesis of Data-Dominated Circuits for Minimal Energy Implementation. VLSI Design 2005: 267-273 |
7 | EE | Xiaoyong Tang, Tianyi Jiang, Alex K. Jones, Prithviraj Banerjee: High-Level Synthesis for Low Power Hardware Implementation of Unscheduled Data-Dominated Circuits. J. Low Power Electronics 1(3): 259-272 (2005) |
6 | EE | Raymond R. Hoare, Zhu Ding, Shen Chih Tung, Rami G. Melhem, Alex K. Jones: A framework for the design, synthesis and cycle-accurate simulation of multiprocessor networks. J. Parallel Distrib. Comput. 65(10): 1237-1252 (2005) |
2004 | ||
5 | EE | Rajarshi Mukherjee, Alex K. Jones, Prithviraj Banerjee: Handling Data Streams while Compiling C Programs onto Hardware. ISVLSI 2004: 271-272 |
2003 | ||
4 | EE | Alex K. Jones, Prithviraj Banerjee: An Automated and Power-Aware Framework for Utilization of IP Cores in Hardware Generated from C Descriptions Targeting FPGAs. FCCM 2003: 284-285 |
3 | EE | Alex K. Jones, Prithviraj Banerjee: An automated and power-aware framework for utilization of IP cores in hardware generated from C descriptions targeting FPGAs. FPGA 2003: 244 |
2002 | ||
2 | EE | Alex K. Jones, Debabrata Bagchi, Satrajit Pal, Xiaoyong Tang, Alok N. Choudhary, Prithviraj Banerjee: PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations. CASES 2002: 188-197 |
2000 | ||
1 | EE | Prithviraj Banerjee, U. Nagaraj Shenoy, Alok N. Choudhary, Scott Hauck, C. Bachmann, Malay Haldar, Pramod G. Joisha, Alex K. Jones, Abhay Kanhere, Anshuman Nayak, S. Periyacheri, M. Walkden, David Zaretsky: A MATLAB Compiler for Distributed, Heterogeneous, Reconfigurable Computing Systems. FCCM 2000: 39-48 |