| 1996 |
|---|
| 7 | EE | Zaifu Zhang,
Robert D. McLeod:
An Efficient Multiple Scan Chain Testing Scheme.
Great Lakes Symposium on VLSI 1996: 294- |
| 6 | EE | Zaifu Zhang,
Robert D. McLeod,
Gregory E. Bridges:
Statistical estimation of delay fault detectabilities and fault grading.
J. Electronic Testing 8(1): 47-60 (1996) |
| 1995 |
|---|
| 5 | EE | Richard W. Wieler,
Zaifu Zhang,
Robert D. McLeod:
Emulating static faults using a Xilinx based emulator.
FCCM 1995: 110-115 |
| 4 | EE | Zaifu Zhang,
Robert D. McLeod,
Gregory E. Bridges:
Statistical estimation of delay fault detectabilities and fault grading.
Great Lakes Symposium on VLSI 1995: 184-187 |
| 1994 |
|---|
| 3 | | Zaifu Zhang,
Robert D. McLeod,
Witold Pedrycz:
Augmenting Scan Path SRLs with an XOR Network to Enhance Delay Fault Testing.
DFT 1994: 55-64 |
| 2 | | Richard W. Wieler,
Zaifu Zhang,
Robert D. McLeod:
Simulating Static and Dynamic Faults in BIST Strucutres with a FPGA Based Emulator.
FPL 1994: 240-250 |
| 1993 |
|---|
| 1 | EE | Zaifu Zhang,
Robert D. McLeod,
Witold Pedrycz:
A neural network algorithm for testing stuck-open faults in CMOS combinational circuits.
J. Electronic Testing 4(3): 225-235 (1993) |
