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Yun-Nan Chang

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2008
8EEYun-Nan Chang, Ting-Chi Tong: An Efficient Design of H.264 Inter Interpolator with Bandwidth Optimization. Signal Processing Systems 53(3): 435-448 (2008)
2005
7EEYun-Nan Chang: Design of an efficient memory-based DVB-T channel decoder. ISCAS (5) 2005: 5019-5022
2003
6EEYun-Nan Chang: Design of soft-output Viterbi decoders with hybrid trace-back processing. ISCAS (2) 2003: 69-72
5EEYun-Nan Chang: An Efficient In-Place VLSI Architecture for Viterbi Algorithm. VLSI Signal Processing 33(3): 317-324 (2003)
1998
4EEYun-Nan Chang, Ching-Yi Wang, Keshab K. Parhi: Heuristic Loop-Based Scheduling and Allocation for DSP Synthesis with Heterogeneous Functional Units. VLSI Signal Processing 19(3): 243-256 (1998)
1997
3 Yun-Nan Chang, Janardhan H. Satyanarayana, Keshab K. Parhi: Design and Implementation of Low-Power Digit-Serial Multipliers. ICCD 1997: 186-195
1996
2EEYun-Nan Chang, Ching-Yi Wang, Keshab K. Parhi: Loop-List Scheduling for Heterogeneous Functional Units. Great Lakes Symposium on VLSI 1996: 2-7
1EEJanardhan H. Satyanarayana, Keshab K. Parhi, Leilei Song, Yun-Nan Chang: Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers. ICCD 1996: 492-499

Coauthor Index

1Keshab K. Parhi [1] [2] [3] [4]
2Janardhan H. Satyanarayana [1] [3]
3Leilei Song [1]
4Ting-Chi Tong [8]
5Ching-Yi Wang [2] [4]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)