| 2007 |
|---|
| 10 | | Hsiang-Ling Jamie Lin,
Jabulani Nyathi,
Clint Cole:
Evaluation of CPU Utilization Under a Hardware-software Partitioned Enviroment (Migrating Software to Hardware).
ESA 2007: 222-228 |
| 2006 |
|---|
| 9 | | Kamini Prajapati,
Jabulani Nyathi:
An Efficient Key Update Scheme For Wireless Sensor Networks.
ICWN 2006: 8-14 |
| 8 | EE | Jabulani Nyathi,
Brent Bero:
Logic circuits operating in subthreshold voltages.
ISLPED 2006: 131-134 |
| 2005 |
|---|
| 7 | EE | Valeriu Beiu,
Snorre Aunet,
Jabulani Nyathi,
Ray Robert Rydberg III,
Asbjørn Djupdal:
On the Advantages of Serial Architectures for Low-Power Reliable Computations.
ASAP 2005: 276-281 |
| 6 | EE | Ray Robert Rydberg III,
Jabulani Nyathi,
José G. Delgado-Frias:
A distributed FIFO scheme for on chip communication.
ISCAS (2) 2005: 1851-1854 |
| 2004 |
|---|
| 5 | | James Levy,
Jabulani Nyathi:
A High Performance, Low Area Overhead Carry Lookahead Adder.
ESA/VLSI 2004: 417-426 |
| 4 | | Ray Robert Rydberg III,
Jabulani Nyathi,
José G. Delgado-Frias:
A Distributed FIFO Scheme for System on Chip Inter-Component Communication.
ESA/VLSI 2004: 536-540 |
| 2000 |
|---|
| 3 | EE | José G. Delgado-Frias,
Jabulani Nyathi,
Laxmi N. Bhuyan:
A wave-pipelined router architecture using ternary associative memory.
ACM Great Lakes Symposium on VLSI 2000: 67-70 |
| 1998 |
|---|
| 2 | EE | José G. Delgado-Frias,
Jabulani Nyathi:
A VLSI High-Performance Encoder with Priority Lookahead.
Great Lakes Symposium on VLSI 1998: 59-64 |
| 1996 |
|---|
| 1 | EE | José G. Delgado-Frias,
Jabulani Nyathi,
Chester L. Miller,
Douglas H. Summerville:
A VLSI Interconnection Network Router Using a D-CAM with Hidden Refresh.
Great Lakes Symposium on VLSI 1996: 246-251 |
