| 2008 |
|---|
| 9 | EE | Sheayun Lee,
Insik Shin,
Woonseok Kim,
Insup Lee,
Sang Lyul Min:
A design framework for real-time embedded systems with code size and energy constraints.
ACM Trans. Embedded Comput. Syst. 7(2): (2008) |
| 2007 |
|---|
| 8 | EE | Sheayun Lee,
Jaejin Lee,
Chang Yun Park,
Sang Lyul Min:
Selective code transformation for dual instruction set processors.
ACM Trans. Embedded Comput. Syst. 6(2): (2007) |
| 2006 |
|---|
| 7 | EE | Sungpack Hong,
Sungjoo Yoo,
Sheayun Lee,
Sangwoo Lee,
Hye Jeong Nam,
Bum-Seok Yoo,
Jaehyung Hwang,
Donghyun Song,
Janghwan Kim,
Jeongeun Kim,
HoonSang Jin,
Kyu-Myung Choi,
Jeong-Taek Kong,
Soo-Kwan Eo:
Creation and utilization of a virtual platform for embedded software optimization: : an industrial case study.
CODES+ISSS 2006: 235-240 |
| 2004 |
|---|
| 6 | EE | Sheayun Lee,
Jaejin Lee,
Chang Yun Park,
Sang Lyul Min:
A Flexible Tradeoff Between Code Size and WCET Using a Dual Instruction Set Processor.
SCOPES 2004: 244-258 |
| 2003 |
|---|
| 5 | EE | Sheayun Lee,
Jaejin Lee,
Sang Lyul Min,
Jason Hiser,
Jack W. Davidson:
Code Generation for a Dual Instruction Set Processor Based on Selective Code Transformation.
SCOPES 2003: 33-48 |
| 4 | | Sheayun Lee,
Jaejin Lee,
Chang Yun Park,
Sang Lyul Min:
A Flexible Tradeoff between Code Size and WCET Employing Dual Instruction Set Processors.
WCET 2003: 91-94 |
| 2001 |
|---|
| 3 | | Sheayun Lee,
Andreas Ermedahl,
Sang Lyul Min,
Naehyuck Chang:
An Accurate Instruction-Level Energy Consumption Model for Embedded RISC Processors.
LCTES/OM 2001: 1-10 |
| 1999 |
|---|
| 2 | | Sheayun Lee,
Sang Lyul Min,
Chong-Sang Kim,
Chang-Gun Lee,
Minsuk Lee:
Cache-Conscious Limited Preemptive Scheduling.
Real-Time Systems 17(2-3): 257-282 (1999) |
| 1998 |
|---|
| 1 | EE | Sheayun Lee,
Chang-Gun Lee,
Minsuk Lee,
Sang Lyul Min,
Chong-Sang Kim:
Limited Preemptible Scheduling to Embrace Cache Memory in Real-Time Systems.
LCTES 1998: 51-64 |
