2006 |
6 | EE | Pier Stanislao Paolucci,
Ahmed Amine Jerraya,
Rainer Leupers,
Lothar Thiele,
Piero Vicini:
SHAPES: : a tiled scalable software hardware architecture platform for embedded systems.
CODES+ISSS 2006: 167-172 |
5 | EE | Francesco Belletti,
Sebastiano Fabio Schifano,
Raffaele Tripiccione,
François Bodin,
Philippe Boucaud,
Jacques Micheli,
Olivier Pène,
Nicola Cabibbo,
Sergio de Luca,
Alessandro Lonardo,
Davide Rossetti,
Piero Vicini,
Maxim Lukyanov,
Laurent Morin,
Norbert Paschedag,
Hubert Simma,
Vincent Morenas,
Dirk Pleiter,
Federico Rapuano:
Computing for LQCD: apeNEXT.
Computing in Science and Engineering 8(1): 18-29 (2006) |
2004 |
4 | EE | R. Ammendola,
M. Guagnelli,
G. Mazza,
F. Palombi,
R. Petronzio,
Davide Rossetti,
A. Salamon,
Piero Vicini:
APENet: a high speed, low latency 3D interconnect network.
CLUSTER 2004: 481 |
2003 |
3 | | François Bodin,
Philippe Boucaud,
Nicola Cabibbo,
F. Di Carlo,
R. De Pietri,
F. Di Renzo,
H. Kaldass,
Alessandro Lonardo,
Maxim Lukyanov,
Sergio de Luca,
Jacques Micheli,
Vincent Morenas,
Norbert Paschedag,
Olivier Pène,
Dirk Pleiter,
Federico Rapuano,
L. Sartori,
Sebastiano Fabio Schifano,
Hubert Simma,
Raffaele Tripiccione,
Piero Vicini:
apeNEXT: a Multi-TFlops Computer for Elementary Particle Physics.
PARCO 2003: 355-362 |
1997 |
2 | | F. Aglietti,
A. Bartolini,
Claudia Battista,
Simone Cabasino,
M. Cosimi,
A. Michelotti,
A. Monello,
Emanuele Panizzi,
Pier Stanislao Paolucci,
W. Rinaldi,
Davide Rossetti,
Hubert Simma,
Mario Torelli,
Piero Vicini,
Nicola Cabibbo,
E. Centurioni,
W. Errico,
F. Laico,
G. Magazzù,
Raffaele Tripiccione:
The Teraflop Parallel Computer APEmille.
HPCN Europe 1997: 991-993 |
1993 |
1 | EE | Claudia Battista,
Simone Cabasino,
Francesco Marzano,
Pier Stanislao Paolucci,
Jarda Pech,
Federico Rapuano,
Renata Sarno,
Gian Marco Todesco,
Mario Torelli,
Walter Tross,
Piero Vicini,
Nicola Cabibbo,
Enzo Marinari,
Giorgio Parisi,
Gaetano Salina,
Filippo del Prete,
Adriano Lai,
Maria Paola Lombardo,
Raffaele Tripiccione,
Adolfo Fucci:
The APE-100 Computer: (I) the Architecture.
International Journal of High Speed Computing 5(4): 637-656 (1993) |