| |
| 1999 | ||
|---|---|---|
| 4 | EE | Jue Wu, Gary S. Greenstein, Elizabeth M. Rudnick: A Fault List Reduction Approach for Efficient Bridge Fault Diagnosis. DATE 1999: 780-781 |
| 1997 | ||
| 3 | EE | Elizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein, Thomas M. Niermann: A genetic algorithm framework for test generation. IEEE Trans. on CAD of Integrated Circuits and Systems 16(9): 1034-1044 (1997) |
| 1994 | ||
| 2 | EE | Elizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein, Thomas M. Niermann: Sequential Circuit Test Generation in a Genetic Algorithm Framework. DAC 1994: 698-704 |
| 1992 | ||
| 1 | EE | Gary S. Greenstein, Janak H. Patel: E-PROOFS: a CMOS bridging fault simulator. ICCAD 1992: 268-271 |
| 1 | Thomas M. Niermann | [2] [3] |
| 2 | Janak H. Patel | [1] [2] [3] |
| 3 | Elizabeth M. Rudnick | [2] [3] [4] |
| 4 | Jue Wu | [4] |