MTDT 2000:
San Jose,
CA,
USA
8th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2000), 7-8 August 2000, San Jose, CA, USA.
IEEE Computer Society 2000, ISBN 0-7695-0689-5 BibTeX
@proceedings{DBLP:conf/mtdt/2000,
title = {8th IEEE International Workshop on Memory Technology, Design,
and Testing (MTDT 2000), 7-8 August 2000, San Jose, CA, USA},
booktitle = {MTDT},
publisher = {IEEE Computer Society},
year = {2000},
isbn = {0-7695-0689-5},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Failure Mechanism/Defects
Flash/EEPROM Design
- Rino Micheloni, Matteo Zammattio, Giovanni Campardo, Osama Khouri, Guido Torelli:
Hierarchical Sector Biasing Organization for Flash Memories.
29-33
Electronic Edition (link) BibTeX
- Osama Khouri, Rino Micheloni, Stefano Gregori, Guido Torelli:
Fast Voltage Regulator for Multilevel Flash Memories.
34-38
Electronic Edition (link) BibTeX
- Jean Michel Daga, Caroline Papaix, Marc Merandat, Stephane Ricard, Giuseppe Medulla, Jeanine Guichaoua, Daniel Auvergne:
Design Techniques for Embedded EEPROM Memories in Portable ASIC and ASSP Solutions.
39-46
Electronic Edition (link) BibTeX
New Ideas
Test and Yield
Memory Testing and Built-in Self-Test
Memory Design
- Wen-Tsong Shiue:
Optimizing Memory Bandwidth with ILP Based Memory Exploration and Assignment for Low Power Embedded Systems.
95-100
Electronic Edition (link) BibTeX
- Valerie Lines, Abdullah Ahmed, Peter Ma, Stanley Ma, Robert McKenzie, Hong-Seok Kim, Cynthia Mar:
66MHz 2.3M Ternary Dynamic Content Addressable Memory.
101-105
Electronic Edition (link) BibTeX
- C. Frey, F. Genevaux, C. Issartel, D. Turgis, Jean-Pierre Schoellkopf:
A Low Voltage Embedded Single Port SRAM Generator in a 0.18µm Standard CMOS Process.
106-112
Electronic Edition (link) BibTeX
Diagnosis
Copyright © Sat May 16 23:30:58 2009
by Michael Ley (ley@uni-trier.de)
