2005 |
9 | EE | Richard E. Matick,
Stanley Schuster:
Logic-based eDRAM: Origins and rationale for use.
IBM Journal of Research and Development 49(1): 145-166 (2005) |
2003 |
8 | EE | David H. Albonesi,
Rajeev Balasubramonian,
Steve Dropsho,
Sandhya Dwarkadas,
Eby G. Friedman,
Michael C. Huang,
Volkan Kursun,
Grigorios Magklis,
Michael L. Scott,
Greg Semeraro,
Pradip Bose,
Alper Buyuktosunoglu,
Peter W. Cook,
Stanley Schuster:
Dynamically Tuning Processor Resources with Adaptive Processing.
IEEE Computer 36(12): 49-58 (2003) |
2002 |
7 | EE | Hans M. Jacobson,
Prabhakar Kudva,
Pradip Bose,
Peter W. Cook,
Stanley Schuster:
Synchronous Interlocked Pipelines.
ASYNC 2002: 3-12 |
6 | EE | Alper Buyuktosunoglu,
David H. Albonesi,
Pradip Bose,
Peter W. Cook,
Stanley Schuster:
Tradeoffs in power-efficient issue queue design.
ISLPED 2002: 184-189 |
5 | EE | Pradip Bose,
David Brooks,
Alper Buyuktosunoglu,
Peter W. Cook,
K. Das,
Philip G. Emma,
Michael Gschwind,
Hans M. Jacobson,
Tejas Karkhanis,
Prabhakar Kudva,
Stanley Schuster,
James E. Smith,
Viji Srinivasan,
Victor V. Zyuban,
David H. Albonesi,
Sandhya Dwarkadas:
Early-Stage Definition of LPX: A Low Power Issue-Execute Processor.
PACS 2002: 1-17 |
2001 |
4 | EE | Alper Buyuktosunoglu,
David H. Albonesi,
Stanley Schuster,
David Brooks,
Pradip Bose,
Peter W. Cook:
A circuit level implementation of an adaptive issue queue for power-aware microprocessors.
ACM Great Lakes Symposium on VLSI 2001: 73-78 |
2000 |
3 | EE | Alper Buyuktosunoglu,
Stanley Schuster,
David Brooks,
Pradip Bose,
Peter W. Cook,
David H. Albonesi:
An Adaptive Issue Queue for Reduced Power at High Performance.
PACS 2000: 25-39 |
2 | EE | D. L. Critchlow,
Robert H. Dennard,
Stanley Schuster:
Design and characteristics of n-channel insulated-gate field-effect transistors.
IBM Journal of Research and Development 44(1): 70-83 (2000) |
1 | EE | David Brooks,
Pradip Bose,
Stanley Schuster,
Hans M. Jacobson,
Prabhakar Kudva,
Alper Buyuktosunoglu,
John-David Wellman,
Victor V. Zyuban,
Manish Gupta,
Peter W. Cook:
Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors.
IEEE Micro 20(6): 26-44 (2000) |