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Rajeev Balasubramonian

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2009
22EEManu Awasthi, Kshitij Sudan, Rajeev Balasubramonian, John B. Carter: Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches. HPCA 2009: 250-261
21EENiti Madan, Li Zhao, Naveen Muralimanohar, Aniruddha Udipi, Rajeev Balasubramonian, Ravishankar Iyer, Srihari Makineni, Donald Newell: Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy. HPCA 2009: 262-274
2008
20EESeth H. Pugsley, Manu Awasthi, Niti Madan, Naveen Muralimanohar, Rajeev Balasubramonian: Scalable and reliable communication for hardware transactional memory. PACT 2008: 144-154
19EENaveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi: Architecting Efficient Interconnects for Large Caches with CACTI 6.0. IEEE Micro 28(1): 69-79 (2008)
2007
18EENaveen Muralimanohar, Rajeev Balasubramonian: Interconnect design considerations for large NUCA caches. ISCA 2007: 369-380
17EENiti Madan, Rajeev Balasubramonian: Leveraging 3D Technology for Improved Reliability. MICRO 2007: 223-235
16EENaveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi: Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0. MICRO 2007: 3-14
15EENiti Madan, Rajeev Balasubramonian: Power Efficient Approaches to Redundant Multithreading. IEEE Trans. Parallel Distrib. Syst. 18(8): 1066-1079 (2007)
2006
14EELiqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, John B. Carter: Interconnect-Aware Coherence Protocols for Chip Multiprocessors. ISCA 2006: 339-351
13EENaveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian: Power efficient resource scaling in partitioned architectures through dynamic heterogeneity. ISPASS 2006: 100-111
12EERajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Liqun Cheng, John B. Carter: Leveraging Wire Properties at the Microarchitecture Level. IEEE Micro 26(6): 40-52 (2006)
2005
11EERajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Venkatanand Venkatachalapathy: Microarchitectural Wire Management for Performance and Power in Partitioned Architectures. HPCA 2005: 28-39
2004
10EERajeev Balasubramonian: Cluster prefetch: tolerating on-chip wire delays in clustered microarchitectures. ICS 2004: 326-335
2003
9EERajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi: Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors. ISCA 2003: 275-286
8EERajeev Balasubramonian, Viji Srinivasan, Sandhya Dwarkadas, Alper Buyuktosunoglu: Hot-and-Cold: Using Criticality in the Design of Energy-Efficient Caches. PACS 2003: 180-195
7EEDavid H. Albonesi, Rajeev Balasubramonian, Steve Dropsho, Sandhya Dwarkadas, Eby G. Friedman, Michael C. Huang, Volkan Kursun, Grigorios Magklis, Michael L. Scott, Greg Semeraro, Pradip Bose, Alper Buyuktosunoglu, Peter W. Cook, Stanley Schuster: Dynamically Tuning Processor Resources with Adaptive Processing. IEEE Computer 36(12): 49-58 (2003)
6EERajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas: A Dynamically Tunable Memory Hierarchy. IEEE Trans. Computers 52(10): 1243-1258 (2003)
2002
5EEGreg Semeraro, Grigorios Magklis, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, Michael L. Scott: Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling. HPCA 2002: 29-42
4EESteve Dropsho, Alper Buyuktosunoglu, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, Greg Semeraro, Grigorios Magklis, Michael L. Scott: Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power. IEEE PACT 2002: 141-
2001
3EERajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi: Dynamically allocating processor resources between nearby and distant ILP. ISCA 2001: 26-37
2EERajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi: Reducing the complexity of the register file in dynamic superscalar processors. MICRO 2001: 237-248
2000
1EERajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas: Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures. MICRO 2000: 245-257

Coauthor Index

1David H. Albonesi [1] [2] [3] [4] [5] [6] [7] [9]
2Manu Awasthi [20] [22]
3Pradip Bose [7]
4Alper Buyuktosunoglu [1] [4] [6] [7] [8]
5John B. Carter [12] [14] [22]
6Liqun Cheng [12] [14]
7Peter W. Cook [7]
8Steven G. Dropsho (Steve Dropsho) [4] [7]
9Sandhya Dwarkadas [1] [2] [3] [4] [5] [6] [7] [8] [9]
10Eby G. Friedman [7]
11Michael C. Huang [7]
12Ravishankar Iyer [21]
13Norman P. Jouppi [16] [19]
14Volkan Kursun [7]
15Niti Madan [15] [17] [20] [21]
16Grigorios Magklis [4] [5] [7]
17Srihari Makineni [21]
18Naveen Muralimanohar [11] [12] [13] [14] [16] [18] [19] [20] [21]
19Donald Newell [21]
20Seth H. Pugsley [20]
21Karthik Ramani [11] [12] [13] [14]
22Stanley Schuster [7]
23Michael L. Scott [4] [5] [7]
24Greg Semeraro [4] [5] [7]
25Viji Srinivasan [8]
26Kshitij Sudan [22]
27Aniruddha Udipi [21]
28Venkatanand Venkatachalapathy [11]
29Li Zhao [21]

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Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)