Valeriu Beiu

2008
30	EE	Valeriu Beiu, Walid Ibrahim: Does the brain really outperform Rent's rule? ISCAS 2008: 640-643
2007
29	EE	Walid Ibrahim, Valeriu Beiu: Long Live Small Fan-in Majority Gates Their Reign Looks Like Coming! ASAP 2007: 278-283
28	EE	Valeriu Beiu: Grand Challenges of Nanoelectronics and Possible Architectural Solutions: What Do Shannon, von Neumann, Kolmogorov, and Feynman Have to do with Moore. ISMVL 2007
27	EE	Valeriu Beiu, Walid Ibrahim, Sanja Lazarova-Molnar: What von Neumann Did Not Say About Multiplexing Beyond Gate Failures - The Gory Details. IWANN 2007: 487-496
2005
26	EE	Valeriu Beiu, Snorre Aunet, Jabulani Nyathi, Ray Robert Rydberg III, Asbjørn Djupdal: On the Advantages of Serial Architectures for Low-Power Reliable Computations. ASAP 2005: 276-281
25	EE	Valeriu Beiu, Artur Zawadski, Razvan Andonie, Snorre Aunet: Using Kolmogorov Inspired Gates for Low Power Nanoelectronics. IWANN 2005: 438-445
24	EE	Valeriu Beiu, Asbjørn Djupdal, Snorre Aunet: Ultra Low-Power Neural Inspired Addition: When Serial Might Outperform Parallel Architectures. IWANN 2005: 486-493
2004
23	EE	Valeriu Beiu: A Novel Highly Reliable Low-Power Nano Architecture When von Neumann Augments. ASAP 2004: 167-177
22		David J. Betowski, Daniel Dwyer, Valeriu Beiu: A Novel Segmented Parabolic Sine Approximation for Direct Digital Frequency Synthesizers. ESA/VLSI 2004: 523-529
21		Valeriu Beiu, Mawahib Sulieman: Optimal Practical Perceptron Addition Application to Single Electron Technology. ESA/VLSI 2004: 541-550
20	EE	Mawahib Sulieman, Valeriu Beiu: Characterization of a 16-bit threshold logic single-electron technology adder. ISCAS (3) 2004: 681-684
2003
19	EE	Valeriu Beiu, Maria J. Avedillo, José M. Quintana: Review of Capacitive Threshold Gate Implementations. ICANN 2003: 737-744
18	EE	Valeriu Beiu: Constructive Threshold Logic Addition A Synopsis of the Last Decade. ICANN 2003: 745-752
17	EE	Suryanarayana Tatapudi, Valeriu Beiu: Split-Precharge Differential Noise-Immune Threshold Logic Gate (SPD-NTL). IWANN (2) 2003: 49-56
16		Razvan Andonie, Lucian Sasu, Valeriu Beiu: A Modified Fuzzy ARTMAP Architecture for Incremental Learning Function Approximation. Neural Networks and Computational Intelligence 2003: 124-129
15		Valeriu Beiu, José M. Quintana, Maria J. Avedillo: Review of Differential Threshold Gate Implementations. Neural Networks and Computational Intelligence 2003: 44-49
14		Valeriu Beiu: On Existential and Constructive Neural Complexity Results. Neural Networks and Computational Intelligence 2003: 63-72
1999
13		Valeriu Beiu: Neural Addition and Fibonacci Numbers. IWANN (2) 1999: 198-207
12		Valeriu Beiu, Sorin Draghici, Thierry de Pauw: A Constructive Approach to Calculating Lower Entropy Bounds. Neural Processing Letters 9(1): 1-12 (1999)
1998
11		Valeriu Beiu: 2D Neural Hardware versus 3D Biological Ones. NC 1998: 36-42
10	EE	Valeriu Beiu: On Kolmogorov's Superpositions and Boolean Functions. SBRN 1998: 55-60
9		Valeriu Beiu, Hanna E. Makaruk: Deeper Sparsely Nets can be Optimal. Neural Processing Letters 8(3): 201-210 (1998)
8	EE	Valeriu Beiu: On the circuit and VLSI complexity of threshold gate COMPARISON. Neurocomputing 19(1-3): 77-98 (1998)
1997
7	EE	Valeriu Beiu: Enhanced lower entropy bounds with application to constructive learning. EUROMICRO 1997: 541-548
6		Valeriu Beiu, Thierry de Pauw: Tight Bounds on the Size of Neural Networks for Classification Problems. IWANN 1997: 743-752
5	EE	Valeriu Beiu, Sorin Draghici, Hanna E. Makaruk: On limited fan-in optimal neural networks. SBRN 1997: 19-30
1996
4	EE	Valeriu Beiu, John G. Taylor: On the Circuit Complexity of Sigmoid Feedforward Neural Networks. Neural Networks 9(7): 1155-1171 (1996)
1995
3		Valeriu Beiu, John G. Taylor: Optimal Mapping of Neural Networks onto FPGA's - A New Constructive Algorithm -. IWANN 1995: 822-829
1994
2		Valeriu Beiu, J. A. Peperstraete, Joos Vandewalle, Rudy Lauwereins: Closse Approximations of Sigmoid Functions by Sum of Step for VLSI Implementation of Neural Networks. Sci. Ann. Cuza Univ. 3: 5-34 (1994)
1988
1		Valeriu Beiu: VLSI arrays implementing parallel line-drawing algorithms. Parcella 1988: 241-247

Coauthor Index

1	Razvan Andonie	[16] [25]
2	Snorre Aunet	[24] [25] [26]
3	Maria J. Avedillo	[15] [19]
4	David J. Betowski	[22]
5	Asbjørn Djupdal	[24] [26]
6	Sorin Draghici	[5] [12]
7	Daniel Dwyer	[22]
8	Walid Ibrahim	[27] [29] [30]
9	Rudy Lauwereins	[2]
10	Sanja Lazarova-Molnar	[27]
11	Hanna E. Makaruk	[5] [9]
12	Jabulani Nyathi	[26]
13	Thierry de Pauw	[6] [12]
14	J. A. Peperstraete	[2]
15	José M. Quintana	[15] [19]
16	Ray Robert Rydberg III	[26]
17	Lucian Sasu	[16]
18	Mawahib Sulieman	[20] [21]
19	Suryanarayana Tatapudi	[17]
20	John G. Taylor	[3] [4]
21	Joos Vandewalle	[2]
22	Artur Zawadski	[25]

Colors in the list of coauthors