| 2009 |
|---|
| 118 | EE | Xin Fu,
Tao Li,
José A. B. Fortes:
Soft error vulnerability aware process variation mitigation.
HPCA 2009: 93-104 |
| 2008 |
|---|
| 117 | EE | Xin Fu,
Tao Li,
José A. B. Fortes:
Combined circuit and microarchitecture techniques for effective soft error robustness in SMT processors.
DSN 2008: 137-146 |
| 116 | EE | Xin Fu,
Wangyuan Zhang,
Tao Li,
José A. B. Fortes:
Optimizing Issue Queue Reliability to Soft Errors on Simultaneous Multithreaded Architectures.
ICPP 2008: 190-197 |
| 115 | EE | Xin Fu,
Tao Li,
José A. B. Fortes:
NBTI tolerant microarchitecture design in the presence of process variation.
MICRO 2008: 399-410 |
| 114 | EE | Jing Xu,
Ming Zhao,
José A. B. Fortes,
Robert Carpenter,
Mazin S. Yousif:
Autonomic resource management in virtualized data centers using fuzzy logic-based approaches.
Cluster Computing 11(3): 213-227 (2008) |
| 113 | EE | Renato J. O. Figueiredo,
P. Oscar Boykin,
José A. B. Fortes,
Tao Li,
Jie-Kwon Peir,
David Wolinsky,
Lizy Kurian John,
David R. Kaeli,
David J. Lilja,
Sally A. McKee,
Gokhan Memik,
Alain Roy,
Gary S. Tyson:
Archer: A Community Distributed Computing Infrastructure for Computer Architecture Research and Education
CoRR abs/0807.1765: (2008) |
| 2007 |
|---|
| 112 | EE | Andréa M. Matsunaga,
Maurício O. Tsugawa,
José A. B. Fortes:
Integration of text-based applications into service-oriented architectures for transnational digital government.
DG.O 2007: 112-121 |
| 111 | EE | Jing Xu,
Ming Zhao,
José A. B. Fortes,
Robert Carpenter,
Mazin S. Yousif:
On the Use of Fuzzy Modeling in Virtualized Data Center Management.
ICAC 2007: 25 |
| 110 | EE | Wangyuan Zhang,
Xin Fu,
Tao Li,
José A. B. Fortes:
An Analysis of Microarchitecture Vulnerability to Soft Errors on Simultaneous Multithreaded Architectures.
ISPASS 2007: 169-178 |
| 109 | EE | Jack DiGiovanna,
Loris Marchal,
Prapaporn Rattanatamrong,
Ming Zhao,
Shalom Darmanjian,
Babak Mahmoudi,
Justin C. Sanchez,
José C. Príncipe,
Linda Hermer-Vazquez,
Renato J. O. Figueiredo,
José A. B. Fortes:
Towards Real-Time Distributed Signal Modeling for Brain-Machine Interfaces.
International Conference on Computational Science (1) 2007: 964-971 |
| 108 | EE | Andréa M. Matsunaga,
Maurício O. Tsugawa,
Sumalatha Adabala,
Renato J. O. Figueiredo,
Herman Lam,
José A. B. Fortes:
Science gateways made easy: the In-VIGO approach.
Concurrency and Computation: Practice and Experience 19(6): 905-919 (2007) |
| 2006 |
|---|
| 107 | | José A. B. Fortes,
Ann Macintosh:
Proceedings of the 7th Annual International Conference on Digital Government Research, DG.O 2006, San Diego, California, USA, May 21-24, 2006
Digital Government Research Center 2006 |
| 106 | EE | Maurício O. Tsugawa,
Andréa M. Matsunaga,
José A. B. Fortes:
Virtualization technologies in transnational DG.
DG.O 2006: 456-457 |
| 105 | EE | Maurício O. Tsugawa,
José A. B. Fortes:
A virtual network (ViNe) architecture for grid computing.
IPDPS 2006 |
| 104 | EE | José A. B. Fortes:
HCW panel: programming heterogeneous systems - Less pain! Better performance!
IPDPS 2006 |
| 103 | EE | José A. B. Fortes,
Renato J. O. Figueiredo,
Linda Hermer-Vazquez,
José Carlos Príncipe,
Justin C. Sanchez:
A New Architecture for Deriving Dynamic Brain-Machine Interfaces.
International Conference on Computational Science (3) 2006: 546-553 |
| 102 | EE | Xin Fu,
James Poe,
Tao Li,
José A. B. Fortes:
Characterizing Microarchitecture Soft Error Vulnerability Phase Behavior.
MASCOTS 2006: 147-155 |
| 2005 |
|---|
| 101 | EE | Jie Han,
Erin Taylor,
Jianbo Gao,
José A. B. Fortes:
Faults, Error Bounds and Reliability of Nanoelectronic Circuits.
ASAP 2005: 247-253 |
| 100 | EE | José A. B. Fortes:
Transnational digital government research project highlights.
DG.O 2005: 171-172 |
| 99 | EE | Andréa M. Matsunaga,
Maurício O. Tsugawa,
José A. B. Fortes:
Virtual machines in transnational digital government: a case study.
DG.O 2005: 255-256 |
| 98 | EE | Andréa M. Matsunaga,
Maurício O. Tsugawa,
Ming Zhao,
Liping Zhu,
Vivekananthan Sanjeepan,
Sumalatha Adabala,
Renato J. O. Figueiredo,
Herman Lam,
José A. B. Fortes:
On the Use of Virtualization and Service Technologies to Enable Grid-Computing.
Euro-Par 2005: 1-12 |
| 97 | EE | Jing Xu,
Sumalatha Adabala,
José A. B. Fortes:
Towards Autonomic Virtual Applications in the In-VIGO System.
ICAC 2005: 15-26 |
| 96 | EE | Vivekananthan Sanjeepan,
Andréa M. Matsunaga,
Liping Zhu,
Herman Lam,
José A. B. Fortes:
A Service-Oriented, Scalable Approach to Grid-Enabling of Legacy Scientific Applications.
ICWS 2005: 553-560 |
| 95 | EE | Yue Li,
Tao Li,
Tamer Kahveci,
José A. B. Fortes:
Workload Characterization of Bioinformatics Applications.
MASCOTS 2005: 15-22 |
| 94 | EE | Liping Zhu,
Andréa M. Matsunaga,
Vivekananthan Sanjeepan,
Herman Lam,
José A. B. Fortes:
Application Modeling and Representation for Automatic Grid-Enabling of Legacy Applications.
e-Science 2005: 24-31 |
| 93 | EE | Sumalatha Adabala,
Vineet Chadha,
Puneet Chawla,
Renato J. O. Figueiredo,
José A. B. Fortes,
Ivan Krsul,
Andréa M. Matsunaga,
Maurício O. Tsugawa,
Jian Zhang,
Ming Zhao,
Liping Zhu,
Xiaomin Zhu:
From virtualized resources to virtual computing grids: the In-VIGO system.
Future Generation Comp. Syst. 21(6): 896-909 (2005) |
| 92 | EE | Renato J. O. Figueiredo,
Peter A. Dinda,
José A. B. Fortes:
Guest Editors' Introduction: Resource Virtualization Renaissance.
IEEE Computer 38(5): 28-31 (2005) |
| 91 | EE | Jie Han,
Jianbo Gao,
Yan Qi,
Pieter Jonker,
José A. B. Fortes:
Toward Hardware-Redundant, Fault-Tolerant Logic for Nanoelectronics.
IEEE Design & Test of Computers 22(4): 328-339 (2005) |
| 2004 |
|---|
| 90 | EE | S. Su,
José A. B. Fortes,
T. R. Kasad,
M. Patil,
Andréa M. Matsunaga,
Maurício O. Tsugawa,
Violetta Cavalli-Sforza,
Jaime G. Carbonell,
Peter J. Jansen,
W. Ward,
R. Cole,
Donald F. Towsley,
Weifeng Chen,
Annie I. Antón,
Qingfeng He,
C. McSweeney,
L. deBrens,
J. Ventura,
P. Taveras,
R. Connolly,
C. Ortega,
B. Piñeres,
O. Brooks,
M. Herrera:
A Prototype System for Transnational Information Sharing and Process Coordination.
DG.O 2004 |
| 89 | EE | S. Su,
José A. B. Fortes,
T. R. Kasad,
M. Patil,
Andréa M. Matsunaga,
Maurício O. Tsugawa,
Violetta Cavalli-Sforza,
Jaime G. Carbonell,
Peter J. Jansen,
W. Ward,
R. Cole,
Donald F. Towsley,
Weifeng Chen,
Annie I. Antón,
Qingfeng He,
C. McSweeney,
L. deBrens,
J. Ventura,
P. Taveras,
R. Connolly,
C. Ortega,
B. Piñeres,
O. Brooks,
M. Herrera:
A Prototype System for Transnational Information Sharing and Process Coordination: System Demo.
DG.O 2004 |
| 88 | EE | José A. B. Fortes:
Transnational Digital Government Research: Project Highlights.
DG.O 2004 |
| 87 | EE | Wessam Hassanein,
José A. B. Fortes,
Rudolf Eigenmann:
Data forwarding through in-memory precomputation threads.
ICS 2004: 207-216 |
| 86 | EE | Sumalatha Adabala,
Andréa M. Matsunaga,
Maurício O. Tsugawa,
Renato J. O. Figueiredo,
José A. B. Fortes:
Single Sign-On in In-VIGO: Role-Based Access via Delegation Mechanisms Using Short-Lived User Identities.
IPDPS 2004 |
| 85 | EE | José A. B. Fortes:
In-VIGO: Making the Grid Virtually Yours.
NPC 2004: 3 |
| 84 | EE | Ivan Krsul,
Arijit Ganguly,
Jian Zhang,
José A. B. Fortes,
Renato J. O. Figueiredo:
VMPlants: Providing and Managing Virtual Machine Execution Environments for Grid Computing.
SC 2004: 7 |
| 83 | EE | Renato J. O. Figueiredo,
Nirav H. Kapadia,
José A. B. Fortes:
Seamless Access to Decentralized Storage Services in Computational Grids via a Virtual File System.
Cluster Computing 7(2): 113-122 (2004) |
| 2003 |
|---|
| 82 | EE | José A. B. Fortes:
Case Study: Transnational Digital Government Research - Building Regional Partnerships.
DG.O 2003 |
| 81 | EE | Rajesh Subramanyan,
José Miguel-Alonso,
José A. B. Fortes:
A Reconfigurable Monitoring System for Large-Scale Network Computing.
Euro-Par 2003: 98-108 |
| 80 | EE | Renato J. O. Figueiredo,
Peter A. Dinda,
José A. B. Fortes:
A Case For Grid Computing On Virtual Machine.
ICDCS 2003: 550-559 |
| 79 | EE | José A. B. Fortes:
Future Challenges in VLSI Design.
ISVLSI 2003: 5-7 |
| 78 | EE | Hyuk-Jae Lee,
José A. B. Fortes:
Generation of Injective and Reversible Modular Mappings.
IEEE Trans. Parallel Distrib. Syst. 14(1): 1-12 (2003) |
| 77 | EE | Ali Raza Butt,
Sumalatha Adabala,
Nirav H. Kapadia,
Renato J. O. Figueiredo,
José A. B. Fortes:
Grid-computing portals and security issues.
J. Parallel Distrib. Comput. 63(10): 1006-1014 (2003) |
| 2002 |
|---|
| 76 | EE | José A. B. Fortes:
Nanocomputing with Delays.
ASAP 2002: 3- |
| 75 | EE | Sumalatha Adabala,
José A. B. Fortes:
An Online Heuristic for Data Placement in Computer Systems with Active Disks.
ICPP 2002: 219- |
| 74 | EE | Ali Raza Butt,
Sumalatha Adabala,
Nirav H. Kapadia,
Renato J. O. Figueiredo,
José A. B. Fortes:
Fine-Grain Access Control for Securing Shared Resources in Computational Grids.
IPDPS 2002 |
| 2001 |
|---|
| 73 | EE | Dolors Royo,
Luis Díaz de Cerio,
Nirav H. Kapadia,
José A. B. Fortes:
Active Yellow Pages: A Pipelined Resource Management Architecture for Wide-Area Network Computing.
HPDC 2001: 147-157 |
| 72 | EE | Renato J. O. Figueiredo,
Nirav H. Kapadia,
José A. B. Fortes:
The PUNCH Virtual File System: Seamless Access to Decentralized Storage Services in a Computational Grid.
HPDC 2001: 334- |
| 71 | EE | Renato J. O. Figueiredo,
José A. B. Fortes:
Hardware Support for Extracting Coarse-Grain Speculative Parallelism in Distributed Shared-Memory Multiprocesors.
ICPP 2001: 214-226 |
| 70 | | Nirav H. Kapadia,
Renato J. O. Figueiredo,
José A. B. Fortes:
Enhancing the Scalability and Usability of Computational Grids via Logical User Accounts and Virtual.
IPDPS 2001: 82 |
| 69 | EE | Jeffrey P. Bradford,
José A. B. Fortes:
Characterization and Parallelization of Decision-Tree Induction.
J. Parallel Distrib. Comput. 61(3): 322-349 (2001) |
| 2000 |
|---|
| 68 | EE | Renato J. O. Figueiredo,
José A. B. Fortes:
Impact of Heterogeneity on DSM Performance.
HPCA 2000: 26- |
| 67 | EE | Sumalatha Adabala,
Nirav H. Kapadia,
José A. B. Fortes:
Interfacing Wide-Area Network Computing and Cluster Management Software: Condor, DQS and PBS via PUNCH.
HPDC 2000: 306-307 |
| 66 | EE | Rajesh Subramanyan,
José Miguel-Alonso,
José A. B. Fortes:
A Scalable SNMP-Based Distributed Monitoring System For Heterogeneous Network Computing.
SC 2000 |
| 65 | EE | Sumalatha Adabala,
Nirav H. Kapadia,
José A. B. Fortes:
Performance and Interoperability Issues in Incorporating Cluster Management Systems Within a Wide-Area Network-Computing Environment.
SC 2000 |
| 64 | EE | Insung Park,
Nirav H. Kapadia,
Renato J. O. Figueiredo,
Rudolf Eigenmann,
José A. B. Fortes:
Towards an Integrated, Web-executable Parallel Programming Tool Environment.
SC 2000 |
| 63 | EE | Renato J. O. Figueiredo,
Jeffrey P. Bradford,
José A. B. Fortes:
Improving the Performance of Heterogeneous DSMs via Multithreading.
VECPAR 2000: 168-180 |
| 62 | EE | Nirav H. Kapadia,
José A. B. Fortes,
Mark S. Lundstrom:
The Purdue University network-computing hubs: running unmodified simulation tools via the WWW.
ACM Trans. Model. Comput. Simul. 10(1): 39-57 (2000) |
| 61 | EE | Nirav H. Kapadia,
Renato J. O. Figueiredo,
José A. B. Fortes:
PUNCH: Web Portal for Running Tools.
IEEE Micro 20(3): 38-47 (2000) |
| 1999 |
|---|
| 60 | EE | Nirav H. Kapadia,
José A. B. Fortes,
Carla E. Brodley:
Predictive Application-Performance Modeling in a Computational Grid Environment.
HPDC 1999 |
| 59 | | Nirav H. Kapadia,
José A. B. Fortes,
Mark S. Lundstrom:
Statewide Enterprise Computing with the Purdue University Network-Computing Hubs.
ICEIS 1999: 657-664 |
| 58 | | Thomas J. Downar,
Rudolf Eigenmann,
José A. B. Fortes:
Issues and Approaches in Parallel Multi-Component and Multi-Physics Simulations.
PDPTA 1999: 916-922 |
| 57 | | Nirav H. Kapadia,
José A. B. Fortes:
PUNCH: An architecture for Web-enabled wide-area network-computing.
Cluster Computing 2(2): 153-164 (1999) |
| 56 | EE | Hasan Cam,
José A. B. Fortes:
Work-Efficient Routing Algorithms for Rearrangeable Symmetrical Networks.
IEEE Trans. Parallel Distrib. Syst. 10(7): 733-741 (1999) |
| 1998 |
|---|
| 55 | EE | Zina Ben-Miled,
José A. B. Fortes,
Rudolf Eigenmann,
Valerie E. Taylor:
On the Implementation of Broadcast, Scatter and Gather in a Heterogeneous Architecture.
HICSS (3) 1998: 216-225 |
| 54 | EE | Nirav H. Kapadia,
José A. B. Fortes:
On the Design of a Demand-Based Network-Computing System: The Purdue University Network-Computing Hub.
HPDC 1998: 71-80 |
| 53 | | Nirav H. Kapadia,
Carla E. Brodley,
José A. B. Fortes,
Mark S. Lundstrom:
Resource-Usage Prediction for Demand-Based Network-Computing.
SRDS 1998: 372-377 |
| 52 | | Renato J. O. Figueiredo,
José A. B. Fortes,
Zina Ben-Miled:
Spatial Data Locality with Respect to Degree of Parallelism in Processor-and-Memory Hierarchies.
VECPAR 1998: 396-410 |
| 51 | EE | Hyuk-Jae Lee,
José A. B. Fortes:
Automatic Generation of Modular Time-Space Mappings and Data Alignments.
VLSI Signal Processing 19(2): 195-208 (1998) |
| 1997 |
|---|
| 50 | EE | Zina Ben-Miled,
José A. B. Fortes,
Rudolf Eigenmann,
Valerie E. Taylor:
Towards the Design of a Heterogeneous Hierarchical Machine: A Simulation Approach.
Annual Simulation Symposium 1997: 126-136 |
| 49 | EE | Hemal V. Shah,
José A. B. Fortes:
Effects of Dynamic Task Distributions on the Performance of a Class of Irregular Computations.
ICPP 1997: 242- |
| 48 | EE | Hyuk-Jae Lee,
José A. B. Fortes:
Automatic generation of injective modular mappings.
ICPP 1997: 417- |
| 47 | EE | Hyuk-Jae Lee,
James P. Robertson,
José A. B. Fortes:
Generalized Cannon's Algorithm for Parallel Matrix Multiplication.
International Conference on Supercomputing 1997: 44-51 |
| 46 | | Meenakshi A. Kandaswamy,
Valerie E. Taylor,
Rudolf Eigenmann,
José A. B. Fortes:
Implicit Finite Element Applications: A Case for Matching the Number of Processors to the Dynamics of the Program Execution.
PPSC 1997 |
| 45 | | Hyuk-Jae Lee,
José A. B. Fortes:
Communication-Minimal Partitioning and Data Alignment for Affine Nested Loops.
Comput. J. 40(6): 302-310 (1997) |
| 44 | EE | Hemal V. Shah,
José A. B. Fortes:
Efficient techniques for performing an irregular computation on distributed memory machines.
Int. J. Systems Science 28(11): 1101-1113 (1997) |
| 43 | | Hyuk-Jae Lee,
José A. B. Fortes:
Modular Mappings and Data Distribution Independent Computations.
Parallel Processing Letters 7(2): 169-180 (1997) |
| 1996 |
|---|
| 42 | EE | Hyuk-Jae Lee,
José A. B. Fortes:
Automatic Generation of Modular Mappings.
ASAP 1996: 155-164 |
| 41 | EE | José Miguel-Alonso,
Agustin Arruabarrena,
Ramón Beivide,
José A. B. Fortes:
An Empirical Evaluation of Techniques for Parallel Discrete-Event Simulation of Interconnection Networks.
PDP 1996: 219-226 |
| 1995 |
|---|
| 40 | EE | Hyuk-Jae Lee,
José A. B. Fortes:
Data Alignments for Modular Time-Space Mappings of BLAS-like Algorithms.
ASAP 1995: 34- |
| 39 | | Hyuk-Jae Lee,
José A. B. Fortes:
Conditions of Blocked BLAS-like Algorithms for Data Alignment and Communication Minimization.
ICPP (3) 1995: 220-223 |
| 38 | | Nirav H. Kapadia,
José A. B. Fortes:
Block-Row Sparse Matrix-Vector Multiplication on SIMD Machines.
ICPP (3) 1995: 34-41 |
| 37 | | Hemal V. Shah,
José A. B. Fortes:
Relaxation and Hybrid Approaches to Gröbner Basis Computation on Distributed Memory Machines.
ICPP (3) 1995: 68-75 |
| 36 | EE | Hyuk-Jae Lee,
José A. B. Fortes:
Toward data distribution independent parallel matrix multiplication.
IPPS 1995: 436-440 |
| 35 | | Hasan Cam,
José A. B. Fortes:
A Fast VLSI-Efficient Self-Routing Permutation Network.
IEEE Trans. Computers 44(3): 448-453 (1995) |
| 34 | | Hasan Cam,
José A. B. Fortes:
Frames: A Simple Characterization of Permutations Realized by Frequently Used Networks.
IEEE Trans. Computers 44(5): 695-697 (1995) |
| 1994 |
|---|
| 33 | | Josep Llosa,
Mateo Valero,
José A. B. Fortes,
Eduard Ayguadé:
Using Sacks to Organize Registers in VLIW Machines.
CONPAR 1994: 628-639 |
| 32 | | Jordi Cortadella,
José A. B. Fortes,
Edward A. Lee:
Design and Prototyping of Digital Signal Processing (DSP) Systems: Introduction.
HICSS (1) 1994: 56-57 |
| 31 | | James B. Armstrong,
Howard Jay Siegel,
William E. Cohen,
Min Tan,
Henry G. Dietz,
José A. B. Fortes:
Dynamic Task Migration from SPMD to SIMD Virtual Machines.
ICPP 1994: 160-169 |
| 30 | | José A. B. Fortes,
Benjamin W. Wah,
Weijia Shang,
Kumar N. Ganapathy:
Algorithm-Specific Parallel Processing with Linear Processor Arrays.
Advances in Computers 38: 197-245 (1994) |
| 29 | EE | Weijia Shang,
Matthew T. O'Keefe,
José A. B. Fortes:
On Loop Transformations for Generalized Cycle Shrinking.
IEEE Trans. Parallel Distrib. Syst. 5(2): 193-204 (1994) |
| 1993 |
|---|
| 28 | | Gene Saghi,
Howard Jay Siegel,
José A. B. Fortes:
On the Practical Application of a Quantitative Model of System Reconfiguration Due to a Fault.
ICPP 1993: 248-252 |
| 1992 |
|---|
| 27 | | Gene Saghi,
Howard Jay Siegel,
José A. B. Fortes:
On the Viability of a Quantitative Model of System Reconfiguration Due to a Fault.
ICPP (1) 1992: 233-242 |
| 26 | | Hasan Cam,
José A. B. Fortes:
Fault-Tolerant Self-Routing Permutation Networks.
ICPP (1) 1992: 243-247 |
| 25 | | Zhenhui Yang,
Weijia Shang,
José A. B. Fortes:
Conflict-Free Scheduling of Nested Loop Algorithms on Lower Dimensional Processor Arrays.
IPPS 1992: 156-164 |
| 24 | | Matthew T. O'Keefe,
José A. B. Fortes,
Benjamin W. Wah:
On the Relationship Between Two Systolic Array Design Mehodologies.
IEEE Trans. Computers 41(12): 1589-1593 (1992) |
| 23 | | Weijia Shang,
José A. B. Fortes:
Independent Partitioning of Algorithms with Uniform Dependencies.
IEEE Trans. Computers 41(2): 190-206 (1992) |
| 22 | | Darwen Rau,
José A. B. Fortes,
Howard Jay Siegel:
Destination Tag Routing Techniques Based on a State Model for the IADM Network.
IEEE Trans. Computers 41(3): 274-285 (1992) |
| 21 | | Noé Lopez-Benitez,
José A. B. Fortes:
Detailed Modeling and Reliability Analysis of Fault-Tolerant Processor Arrays.
IEEE Trans. Computers 41(9): 1193-1200 (1992) |
| 20 | EE | Weijia Shang,
José A. B. Fortes:
On Time Mapping of Uniform Dependence Algorithms into Lower Dimensional Processor Arrays.
IEEE Trans. Parallel Distrib. Syst. 3(3): 350-363 (1992) |
| 1991 |
|---|
| 19 | | Weijia Shang,
Matthew T. O'Keefe,
José A. B. Fortes:
Generalized cycle shrinking.
Algorithms and Parallel VLSI Architectures 1991: 131-144 |
| 18 | | Weijia Shang,
Matthew T. O'Keefe,
José A. B. Fortes:
On Loop Transformations for Generalized Cycle Shrinking.
ICPP (2) 1991: 132-141 |
| 17 | | Weijia Shang,
José A. B. Fortes:
Time Optimal Linear Schedules for Algorithms with Uniform Dependencies.
IEEE Trans. Computers 40(6): 723-742 (1991) |
| 1990 |
|---|
| 16 | | Weijia Shang,
José A. B. Fortes:
Time-Optimal and Conflict-Free Mappings of Uniform Dependence Algorithms into Lower Dimensional Processor Arrays.
ICPP (1) 1990: 101-110 |
| 15 | | Mengly Chean,
José A. B. Fortes:
A Taxonomy of Reconfiguration Techniques for Fault-Tolerant Processor Arrays.
IEEE Computer 23(1): 55-69 (1990) |
| 14 | | Mengly Chean,
José A. B. Fortes:
The Full-Use-of-Suitable-Spares (FUSS) Approach to Hardware Reconfiguration for Fault-Tolerant Processor Arrays.
IEEE Trans. Computers 39(4): 564-571 (1990) |
| 1989 |
|---|
| 13 | EE | Fernando J. Nuñez,
José A. B. Fortes:
Performance of Connectionist Learning Algorithms on 2-D SIMD Processor Arrays.
NIPS 1989: 810-817 |
| 12 | EE | José A. B. Fortes,
S. Y. Kung:
Introduction.
VLSI Signal Processing 1(2): 93-94 (1989) |
| 11 | EE | Weijia Shang,
José A. B. Fortes:
On the optimality of linear schedules.
VLSI Signal Processing 1(3): 209-220 (1989) |
| 1988 |
|---|
| 10 | | Weijia Shang,
José A. B. Fortes:
Independent Partitioning of Algorithms With Uniform Data Dependencies.
ICPP (2) 1988: 26-33 |
| 9 | | Darwen Rau,
José A. B. Fortes,
Howard Jay Siegel:
Destination Tag Routing Techniques Based on a State Model for the IADM Network.
ISCA 1988: 318-324 |
| 8 | | William W. Carlson,
José A. B. Fortes:
On the Performance of Combined Data Flow and Control Flow Systems: Experiments Using Two Iterative Algorithms.
J. Parallel Distrib. Comput. 5(4): 359-382 (1988) |
| 1987 |
|---|
| 7 | | William W. Carlson,
José A. B. Fortes:
On the Performance of Combined Data Flow and Control Flow Systems: Experiments Using Two Iterative Algorithms.
ICPP 1987: 671-679 |
| 1986 |
|---|
| 6 | | José A. B. Fortes,
M. Arif Samad:
DEFT: A Design for Testability Expert System.
FJCC 1986: 899-908 |
| 5 | | Matthew T. O'Keefe,
José A. B. Fortes:
A Comparative Study of Two Systematic Design Methodologies for Systolic Arrays.
ICPP 1986: 672-675 |
| 4 | | M. Arif Samad,
José A. B. Fortes:
Explanation Capabilities in DEFT : A Design-For-Testability Expert System.
ITC 1986: 954-963 |
| 3 | | Dan I. Moldovan,
José A. B. Fortes:
Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays.
IEEE Trans. Computers 35(1): 1-12 (1986) |
| 1985 |
|---|
| 2 | | José A. B. Fortes,
C. S. Raghavendra:
Gracefully Degradable Processor Arrays.
IEEE Trans. Computers 34(11): 1033-1044 (1985) |
| 1984 |
|---|
| 1 | | José A. B. Fortes,
Dan I. Moldovan:
Data Broadcasting in Linearly Scheduled Array Processors.
ISCA 1984: 224-231 |
