| 2006 |
|---|
| 5 | EE | Toshihiro Hattori,
Takahiro Irita,
Masayuki Ito,
Eiji Yamamoto,
Hisashi Kato,
Go Sado,
Tetsuhiro Yamada,
Kunihiko Nishiyama,
Hiroshi Yagi,
Takao Koike,
Yoshihiko Tsuchihashi,
Motoki Higashida,
Hiroyuki Asano,
Izumi Hayashibara,
Ken Tatezawa,
Yasuhisa Shimazaki,
Naozumi Morino,
Yoshihiko Yasu,
Tadashi Hoshi,
Yujiro Miyairi,
Kazumasa Yanagisawa,
Kenji Hirose,
Saneaki Tamaki,
Shinichi Yoshioka,
Toshifumi Ishii,
Yusuke Kanno,
Hiroyuki Mizuno,
Tetsuya Yamada,
Naohiko Irie,
Reiko Tsuchihashi,
Nobuto Arai,
Tomohiro Akiyama,
Koji Ohno:
Hierarchical power distribution and power management scheme for a single chip mobile processor.
DAC 2006: 292-295 |
| 2001 |
|---|
| 4 | | Kiyoo Itoh,
Hiroyuki Mizuno:
Low-Voltage Embedded-RAM Technology: Present and Future.
VLSI-SOC 2001: 277-288 |
| 1999 |
|---|
| 3 | EE | Koichi Kise,
Hiroyuki Mizuno,
Masashi Yamaguchi,
Keinosuke Matsumoto:
On the Use of Density Distribution of Keywords for Automated Generation of Hypertext Links from Arbitrary Parts of Documents.
ICDAR 1999: 301-304 |
| 2 | EE | Hiroyuki Mizuno,
Koichiro Ishibashi:
A separated bit-line unified cache: Conciliating small on-chip cache die-area and low miss ratio.
IEEE Trans. VLSI Syst. 7(1): 139-144 (1999) |
| 1998 |
|---|
| 1 | EE | Masayuki Miyazaki,
Hiroyuki Mizuno,
Koichiro Ishibashi:
A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSIs.
ISLPED 1998: 48-53 |
