| 2007 |
|---|
| 9 | EE | Yoshihide Komatsu,
Koichiro Ishibashi,
Makoto Nagata:
Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias.
IEICE Transactions 90-C(4): 692-698 (2007) |
| 2006 |
|---|
| 8 | EE | Koichiro Ishibashi,
Tetsuya Fujimoto,
Takahiro Yamashita,
Hiroyuki Okada,
Yukio Arima,
Yasuyuki Hashimoto,
Kohji Sakata,
Isao Minematsu,
Yasuo Itoh,
Haruki Toda,
Motoi Ichihashi,
Yoshihide Komatsu,
Masato Hagiwara,
Toshiro Tsukada:
Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond.
IEICE Transactions 89-C(3): 250-262 (2006) |
| 7 | EE | Yoshihide Komatsu,
Yukio Arima,
Koichiro Ishibashi:
Soft Error Hardened Latch Scheme with Forward Body Bias in a 90-nm Technology and Beyond.
IEICE Transactions 89-C(3): 384-391 (2006) |
| 2005 |
|---|
| 6 | | Yasumasa Tsukamoto,
Koji Nii,
Susumu Imaoka,
Yuji Oda,
Shigeki Ohbayashi,
Tomoaki Yoshizawa,
Hiroshi Makino,
Koichiro Ishibashi,
Hirofumi Shinohara:
Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability.
ICCAD 2005: 398-405 |
| 5 | EE | Takahiro Yamashita,
Tetsuya Fujimoto,
Koichiro Ishibashi:
Power Valve: for low power operation and low stand-by power.
IEICE Electronic Express 2(3): 64-69 (2005) |
| 4 | EE | Koichiro Ishibashi:
Special Section on Low-Power LSI and Low-Power IP.
IEICE Transactions 88-C(4): 467 (2005) |
| 3 | EE | Keisuke Toyama,
Satoshi Misaka,
Kazuo Aisaka,
Toshiyuki Aritsuka,
Kunio Uchiyama,
Koichiro Ishibashi,
Hiroshi Kawaguchi,
Takayasu Sakurai:
Frequency-voltage cooperative CPU power control: A design rule and its application by feedback prediction.
Systems and Computers in Japan 36(6): 39-48 (2005) |
| 1999 |
|---|
| 2 | EE | Hiroyuki Mizuno,
Koichiro Ishibashi:
A separated bit-line unified cache: Conciliating small on-chip cache die-area and low miss ratio.
IEEE Trans. VLSI Syst. 7(1): 139-144 (1999) |
| 1998 |
|---|
| 1 | EE | Masayuki Miyazaki,
Hiroyuki Mizuno,
Koichiro Ishibashi:
A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSIs.
ISLPED 1998: 48-53 |
