| 2003 |
|---|
| 6 | EE | Kyu-won Choi,
Abhijit Chatterjee:
UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSI.
ISLPED 2003: 72-77 |
| 5 | EE | Abdulkadir Utku Diril,
Yuvraj Singh Dhillon,
Kyu-won Choi,
Abhijit Chatterjee:
An O(N)Supply Voltage Assignment Algorithm for Low-Energy Serially Connected CMOS Modules and a Heuristic Extension to Acyclic Data Flow Graphs.
ISVLSI 2003: 173-182 |
| 2002 |
|---|
| 4 | EE | Kyu-won Choi,
Abhijit Chatterjee:
HA2TSD: hierarchical time slack distribution for ultra-low power CMOS VLSI.
ISLPED 2002: 207-212 |
| 3 | EE | Abhijit Chatterjee,
Peeter Ellervee,
Vincent John Mooney III,
Jun-Cheol Park,
Kyu-won Choi,
Kiran Puttaswamy:
System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-Chip Buses and Memory.
ISSS 2002: 225-230 |
| 2 | EE | Kyu-won Choi,
Abhijit Chatterjee:
PA-ZSA (Power-Aware Zero-Slack Algorithm): A Graph-Based Timing Analysis for Ultra-Low Power CMOS VLSI.
PATMOS 2002: 178-187 |
| 2001 |
|---|
| 1 | | Kyu-won Choi,
Abhijit Chatterjee:
Efficient instruction-level optimization methodology for low-power embedded systems.
ISSS 2001: 147-152 |
