| 2005 |
|---|
| 4 | EE | Paul Zuber,
Armin Windschiegl,
Raúl Medina Beltán de Otálora,
Walter Stechele,
Andreas Herkersdorf:
Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization.
DATE 2005: 986-987 |
| 3 | | Paul Zuber,
Florian Helmut Müller,
Walter Stechele:
Optimization Potential of CMOS Power by Wire Spacing.
GI Jahrestagung (1) 2005: 344-348 |
| 2 | EE | Paul Zuber,
Peter Gritzmann,
Michael Ritter,
Walter Stechele:
The Optimal Wire Order for Low Power CMOS.
PATMOS 2005: 674-683 |
| 2002 |
|---|
| 1 | EE | Armin Windschiegl,
Paul Zuber,
Walter Stechele:
Exploiting Metal Layer Characteristics for Low-Power Routing.
PATMOS 2002: 55-64 |
