2007 |
10 | EE | Fernando P. H. de Miranda,
João Navarro Jr.,
Wilhelmus A. M. Van Noije:
A 4.1 GHz Dual Modulus Prescaler Using the E-TSPC Technique and Double Data Throughput Structures.
ISCAS 2007: 1895-1898 |
9 | EE | Hugo Daniel Hernández,
Wilhelmus A. M. Van Noije,
Elkim Roa,
João Navarro Jr.:
A small area 8bits 50MHz CMOS DAC for bluetooth transmitter.
SBCCI 2007: 10-15 |
8 | EE | Fernando P. H. de Miranda,
João Navarro Jr.,
Wilhelmus A. M. Van Noije:
A 4.1 GHz prescaler using double data throughput E-TSPC structures.
SBCCI 2007: 123-127 |
2006 |
7 | EE | A. J. Aragao,
João Navarro Jr.,
Wilhelmus A. M. Van Noije:
Mismatch effect analyses in CMOS tapered buffers.
ISCAS 2006 |
2005 |
6 | EE | Angel M. Gómez Argüello,
João Navarro Jr.,
Wilhelmus A. M. Van Noije:
A 3.5 mW programmable high speed frequency divider for a 2.4 GHz CMOS frequency synthesizer.
SBCCI 2005: 144-148 |
2004 |
5 | EE | Fernando P. H. de Miranda,
João Navarro Jr.,
Wilhelmus A. M. Van Noije:
A 4 GHz dual modulus divider-by 32/33 prescaler in 0.35m CMOS technology.
SBCCI 2004: 94-99 |
2002 |
4 | EE | João Navarro Jr.,
Wilhelmus A. M. Van Noije:
Extended TSPC structures with double input/output data throughput for gigahertz CMOS circuit design.
IEEE Trans. VLSI Syst. 10(3): 301-308 (2002) |
1998 |
3 | EE | João Navarro Jr.,
Wilhelmus A. M. Van Noije:
Design of an 8: 1 MUX at 1.7Gbit/s in 0.8?I`m CMOS Technology.
Great Lakes Symposium on VLSI 1998: 103-107 |
2 | EE | João Navarro Jr.,
Wilhelmus A. M. Van Noije:
CMOS Tapered Buffer Design for Small Width Clock/Data Signal Propagation.
Great Lakes Symposium on VLSI 1998: 89-94 |
1997 |
1 | EE | João Navarro Jr.,
Reinaldo Silveira,
Fábio L. Romao,
Wilhelmus A. M. Van Noije:
A 1.4 Gbit/s CMOS driver for 50 /spl Omega/ ECL systems.
Great Lakes Symposium on VLSI 1997: 14- |