| |
| 1998 | ||
|---|---|---|
| 2 | EE | Kaisheng Wang, Ted Zhihong Yu, Edwin Hsing-Mean Sha: RCRS: A Framework for Loop Scheduling with Limited Number of Registers. Great Lakes Symposium on VLSI 1998: 386-391 |
| 1997 | ||
| 1 | EE | Ted Zhihong Yu, Edwin Hsing-Mean Sha, Nelson L. Passos, Roy Dz-Ching Ju: Algorithm and Hardware Support for Branch Anticipation. Great Lakes Symposium on VLSI 1997: 163- |
| 1 | Roy Dz-Ching Ju (Roy Ju, Dz-Ching Ju) | [1] |
| 2 | Nelson L. Passos | [1] |
| 3 | Edwin Hsing-Mean Sha | [1] [2] |
| 4 | Kaisheng Wang | [2] |