| 2007 |
|---|
| 4 | EE | Subarna Sinha,
Jianfeng Luo,
Charles Chiang:
Model Based Layout Pattern Dependent Metal Filling Algorithm for Improved Chip Surface Uniformity in the Copper Process.
ASP-DAC 2007: 1-6 |
| 3 | EE | Debjit Sinha,
Jianfeng Luo,
Subramanian Rajagopalan,
Shabbir H. Batterywala,
Narendra V. Shenoy,
Hai Zhou:
Impact of Modern Process Technologies on the Electrical Parameters of Interconnects.
VLSI Design 2007: 875-880 |
| 2006 |
|---|
| 2 | EE | Jianfeng Luo,
Subarna Sinha,
Qing Su,
Jamil Kawa,
Charles Chiang:
An IC manufacturing yield model considering intra-die variations.
DAC 2006: 749-754 |
| 2005 |
|---|
| 1 | | Jianfeng Luo,
Qing Su,
Charles Chiang,
Jamil Kawa:
A layout dependent full-chip copper electroplating topography model.
ICCAD 2005: 133-140 |
