2007 |
16 | EE | Brian K. Flachs,
Shigehiro Asano,
Sang H. Dhong,
H. Peter Hofstee,
Gilles Gervais,
Roy Kim,
Tien Le,
Peichun Liu,
Jens Leenstra,
John S. Liberty,
Brad W. Michael,
Hwa-Joon Oh,
Silvia M. Müller,
Osamu Takahashi,
Koji Hirairi,
Atsushi Kawasumi,
Hiroaki Murakami,
Hiromi Noro,
Shoji Onishi,
Juergen Pille,
Joel Silberman,
Suksoon Yong,
Akiyuki Hatakeyama,
Yukio Watanabe,
Naoka Yano,
Daniel A. Brokenshire,
Mohammad Peyravian,
VanDung To,
Eiji Iwata:
Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI.
IBM Journal of Research and Development 51(5): 529-544 (2007) |
15 | EE | Lee Eisen,
John Wesley Ward III,
Hans-Werner Tast,
Nicolas Mäding,
Jens Leenstra,
Silvia M. Müller,
Christian Jacobi,
Jochen Preiss,
Eric M. Schwarz,
Steven R. Carlough:
IBM POWER6 accelerators: VMX and DFU.
IBM Journal of Research and Development 51(6): 663-684 (2007) |
2005 |
14 | EE | Roger A. Golliver,
Silvia M. Müller,
Stuart F. Oberman,
Martin S. Schmookler,
Debjit Das Sarma,
Andrew Beaumont-Smith:
Pain versus Gain in the Hardware Design of FPUs and Supercomputers.
IEEE Symposium on Computer Arithmetic 2005: 39 |
13 | EE | Silvia M. Müller,
Christian Jacobi,
Hwa-Joon Oh,
Kevin D. Tran,
Scott R. Cottier,
Brad W. Michael,
Hiroo Nishikawa,
Yonetaro Totsuka,
Tatsuya Namatame,
Naoka Yano,
Takashi Machida,
Sang H. Dhong:
The Vector Floating-Point Unit in a Synergistic Processor Element of a CELL Processor.
IEEE Symposium on Computer Arithmetic 2005: 59-67 |
2000 |
12 | EE | Silvia M. Müller,
Per Stenström,
Mateo Valero,
Stamatis Vassiliadis:
Parallel Computer Architecture.
Euro-Par 2000: 537-538 |
11 | EE | Guy Even,
Silvia M. Müller,
Peter-Michael Seidel:
A dual precision IEEE floating-point multiplier.
Integration 29(2): 167-180 (2000) |
1999 |
10 | | Silvia M. Müller,
Holger W. Leister,
Peter Dell,
Nikolaus Gerteis,
Daniel Kroening:
The Impact of Hardware Scheduling Mechanismus on the Performance and Cost of Processor Designs.
ARCS 1999: 65-73 |
9 | | Silvia M. Müller:
A Hardware Scheduler for Controlling Variable Latency Functional Units.
Applied Informatics 1999: 581-583 |
8 | EE | Silvia M. Müller:
On the Scheduling of Variable Latency Functional Units.
SPAA 1999: 148-154 |
1998 |
7 | EE | Silvia M. Müller,
Wolfgang J. Paul:
On the Correctness of Hardware Scheduling Mechanisms for Out-of-Order Execution.
Journal of Circuits, Systems, and Computers 8(2): 301-314 (1998) |
1997 |
6 | EE | Silvia M. Müller,
Uzi Vishkin:
Conflict-Free Access to Multiple Single-Ported Register Files.
IPPS 1997: 672-678 |
1996 |
5 | | Silvia M. Müller,
Wolfgang J. Paul:
Making the Original Scoreboard Mechanism Deadlock Free.
ISTCS 1996: 92-99 |
1995 |
4 | | Silvia M. Müller,
Wolfgang J. Paul:
The Complexity of Simple Computer Architectures
Springer 1995 |
1991 |
3 | | Silvia M. Müller,
Dieter Scheerer:
A method to parallelize tridiagonal solvers.
Parallel Computing 17(2-3): 181-188 (1991) |
1989 |
2 | | Silvia M. Müller,
Wolfgang J. Paul:
Contributions of Theoretical Computer Science, Applied Computer Science and Numerical Mathematics to the Design of Parallel Computers.
IFIP Congress 1989: 459-460 |
1988 |
1 | | P. Bergmann,
Jörg Keller,
T. Malter,
Silvia M. Müller,
Wolfgang J. Paul,
Thorsten Pöschel,
O. Schlüter,
L. Thiele:
Implementierung eines informationstheoretischen Ansatzes zur Bilderkennung.
Innovative Informations-Infrastrukturen 1988: 187-197 |