2009 | ||
---|---|---|
52 | EE | Arnaldo Azevedo, Cor Meenderinck, Ben H. H. Juurlink, Andrei Terechko, Jan Hoogerbrugge, Mauricio Alvarez, Alex Ramírez: Parallel H.264 Decoding on an Embedded Multicore Processor. HiPEAC 2009: 404-418 |
51 | EE | Oliverio J. Santana, Ayose Falcón, Alex Ramírez, Mateo Valero: DIA: A Complexity-Effective Decoding Architecture. IEEE Trans. Computers 58(4): 448-462 (2009) |
2008 | ||
50 | Alex Ramírez, Gianfranco Bilardi, Michael Gschwind: Proceedings of the 5th Conference on Computing Frontiers, 2008, Ischia, Italy, May 5-7, 2008 ACM 2008 | |
49 | EE | Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero: MLP-Aware Dynamic Cache Partitioning. HiPEAC 2008: 337-352 |
48 | EE | Carmelo Acosta, Francisco J. Cazorla, Alex Ramírez, Mateo Valero: MFLUSH: Handling Long-Latency Loads in SMT On-Chip Multiprocessors. ICPP 2008: 173-181 |
47 | EE | Arnaldo Azevedo, Cor Meenderinck, Ben H. H. Juurlink, Mauricio Alvarez, Alex Ramírez: Analysis of video filtering on the cell processor. ISCAS 2008: 488-491 |
46 | EE | Sebastian Isaza, Friman Sánchez, Georgi Gaydadjiev, Alex Ramírez, Mateo Valero: Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications. SAMOS 2008: 53-64 |
2007 | ||
45 | EE | Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero: Online Prediction of Applications Cache Utility. ICSAMOS 2007: 169-177 |
44 | EE | Francisco J. Cazorla, Enrique Fernández, Peter M. W. Knijnenburg, Alex Ramírez, Rizos Sakellariou, Mateo Valero: On the Problem of Minimizing Workload Execution Time in SMT Processors. ICSAMOS 2007: 66-73 |
43 | EE | Daniel Jiménez-González, Xavier Martorell, Alex Ramírez: Performance Analysis of Cell Broadband Engine for High Memory Bandwidth Applications. ISPASS 2007: 210-219 |
42 | EE | Mauricio Alvarez, Esther Salamí, Alex Ramírez, Mateo Valero: Performance Impact of Unaligned Memory Operations in SIMD Extensions for Video Codec Applications. ISPASS 2007: 62-71 |
41 | EE | Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero: MLP-Aware Dynamic Cache Partitioning. PACT 2007: 418 |
40 | EE | Paul Carpenter, David Ródenas, Xavier Martorell, Alex Ramírez, Eduard Ayguadé: A Streaming Machine Description and Programming Model. SAMOS 2007: 107-116 |
39 | EE | Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero: Explaining Dynamic Cache Partitioning Speed Ups. Computer Architecture Letters 6(1): 1-4 (2007) |
38 | EE | Oliverio J. Santana, Alex Ramírez, Mateo Valero: Enlarging Instruction Streams. IEEE Trans. Computers 56(10): 1342-1357 (2007) |
37 | EE | Koen De Bosschere, Wayne Luk, Xavier Martorell, Nacho Navarro, Michael F. P. O'Boyle, Dionisios N. Pnevmatikatos, Alex Ramírez, Pascal Sainrat, André Seznec, Per Stenström, Olivier Temam: High-Performance Embedded Architecture and Compilation Roadmap. T. HiPEAC 1: 5-29 (2007) |
2006 | ||
36 | EE | Friman Sánchez, Esther Salamí, Alex Ramírez, Mateo Valero: Performance Analysis of Sequence Alignment Applications. IISWC 2006: 51-60 |
35 | EE | Oliverio J. Santana, Ayose Falcón, Alex Ramírez, Mateo Valero: Branch predictor guided instruction decoding. PACT 2006: 202-211 |
34 | EE | Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero: Predictable Performance in SMT Processors: Synergy between the OS and SMTs. IEEE Trans. Computers 55(7): 785-799 (2006) |
2005 | ||
33 | Nader Bagherzadeh, Mateo Valero, Alex Ramírez: Proceedings of the Second Conference on Computing Frontiers, 2005, Ischia, Italy, May 4-6, 2005 ACM 2005 | |
32 | EE | Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero: Architectural support for real-time task scheduling in SMT processors. CASES 2005: 166-176 |
31 | EE | Carmelo Acosta, Ayose Falcón, Alex Ramírez, Mateo Valero: A Complexity-Effective Simultaneous Multithreading Architecture. ICPP 2005: 157-164 |
30 | EE | Ayose Falcón, Alex Ramírez, Mateo Valero: Effective Instruction Prefetching via Fetch Prestaging. IPDPS 2005 |
29 | EE | Friman Sánchez, Mauricio Alvarez, Esther Salamí, Alex Ramírez, Mateo Valero: On the Scalability of 1- and 2-Dimensional SIMD Extensions for Multimedia Applications. ISPASS 2005: 167-176 |
28 | EE | Ayose Falcón, Jared Stark, Alex Ramírez, Konrad K. Lai, Mateo Valero: Better Branch Prediction Through Prophet/Critic Hybrids. IEEE Micro 25(1): 80-89 (2005) |
27 | EE | Alex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero: Software Trace Cache. IEEE Trans. Computers 54(1): 22-35 (2005) |
2004 | ||
26 | EE | Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero: Predictable performance in SMT processors. Conf. Computing Frontiers 2004: 433-443 |
25 | EE | Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero: Implicit vs. Explicit Resource Allocation in SMT Processors. DSD 2004: 44-51 |
24 | EE | Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero: Feasibility of QoS for SMT. Euro-Par 2004: 535-540 |
23 | EE | Ayose Falcón, Alex Ramírez, Mateo Valero: A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors. HPCA 2004: 244-253 |
22 | EE | Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández: DCache Warn: An I-Fetch Policy to Increase SMT Efficiency. IPDPS 2004 |
21 | EE | Ayose Falcón, Jared Stark, Alex Ramírez, Konrad Lai, Mateo Valero: Prophet/Critic Hybrid Branch Prediction. ISCA 2004: 250-263 |
20 | EE | Oliverio J. Santana, Alex Ramírez, Mateo Valero: Reducing Fetch Architecture Complexity Using Procedure Inlining. Interaction between Compilers and Computer Architectures 2004: 97-106 |
19 | EE | Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández: Dynamically Controlled Resource Allocation in SMT Processors. MICRO 2004: 171-182 |
18 | EE | Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández: QoS for High-Performance SMT Processors in Embedded Systems. IEEE Micro 24(4): 24-31 (2004) |
17 | EE | Ayose Falcón, Oliverio J. Santana, Alex Ramírez, Mateo Valero: A latency-conscious SMT branch prediction architecture. IJHPCN 2(1): 11-21 (2004) |
16 | EE | Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández: Optimising long-latency-load-aware fetch policies for SMT processors. IJHPCN 2(1): 45-54 (2004) |
15 | EE | Oliverio J. Santana, Alex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero: A low-complexity fetch architecture for high-performance superscalar processors. TACO 1(2): 220-245 (2004) |
2003 | ||
14 | EE | Francisco J. Cazorla, Enrique Fernández, Alex Ramírez, Mateo Valero: Improving Memory Latency Aware Fetch Policies for SMT Processors. ISHPC 2003: 70-85 |
13 | EE | Ayose Falcón, Oliverio J. Santana, Alex Ramírez, Mateo Valero: Tolerating Branch Predictor Latency on SMT. ISHPC 2003: 86-98 |
2002 | ||
12 | EE | Hans Vandierendonck, Alex Ramírez, Koenraad De Bosschere, Mateo Valero: A Comparative Study of Redundancy in Trace Caches (Research Note). Euro-Par 2002: 512-516 |
11 | EE | Oliverio J. Santana, Ayose Falcón, Enrique Fernández, Pedro Medina, Alex Ramírez, Mateo Valero: A Comprehensive Analysis of Indirect Branch Prediction. ISHPC 2002: 133-145 |
10 | EE | Ayose Falcón, Oliverio J. Santana, Pedro Medina, Enrique Fernández, Alex Ramírez, Mateo Valero: Studying New Ways for Improving Adaptive History Length Branch Predictors. ISHPC 2002: 271-280 |
9 | EE | Alex Ramírez, Oliverio J. Santana, Josep-Lluis Larriba-Pey, Mateo Valero: Fetching instruction streams. MICRO 2002: 371-382 |
8 | Alex Ramírez, Josep-Lluis Larriba-Pey, Carlos Navarro, Mateo Valero, Josep Torrellas: Software Trace Cache for Commercial Applications. International Journal of Parallel Programming 30(5): 373-395 (2002) | |
2001 | ||
7 | EE | Alex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero: Branch Prediction Using Profile Data. Euro-Par 2001: 386-393 |
6 | EE | Alex Ramírez, Luiz André Barroso, Kourosh Gharachorloo, Robert S. Cohn, Josep-Lluis Larriba-Pey, P. Geoffrey Lowney, Mateo Valero: Code layout optimizations for transaction processing workloads. ISCA 2001: 155-164 |
2000 | ||
5 | EE | Carlos Navarro, Alex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero: On the Performance of Fetch Engines Running DSS Workloads. Euro-Par 2000: 940-949 |
4 | EE | Alex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero: Trace Cache Redundancy: Red & Blue Traces. HPCA 2000: 325- |
3 | EE | Alex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero: The Effect of Code Reordering on Branch Prediction. IEEE PACT 2000: 189-198 |
1999 | ||
2 | EE | Alex Ramírez, Josep-Lluis Larriba-Pey, Carlos Navarro, Xavi Serrano, Mateo Valero, Josep Torrellas: Optimization of Instruction Fetch for Decision Support Workloads. ICPP 1999: 238-245 |
1 | EE | Alex Ramírez, Josep-Lluis Larriba-Pey, Carlos Navarro, Josep Torrellas, Mateo Valero: Software trace cache. International Conference on Supercomputing 1999: 119-126 |