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Alex Ramírez

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2009
52EEArnaldo Azevedo, Cor Meenderinck, Ben H. H. Juurlink, Andrei Terechko, Jan Hoogerbrugge, Mauricio Alvarez, Alex Ramírez: Parallel H.264 Decoding on an Embedded Multicore Processor. HiPEAC 2009: 404-418
51EEOliverio J. Santana, Ayose Falcón, Alex Ramírez, Mateo Valero: DIA: A Complexity-Effective Decoding Architecture. IEEE Trans. Computers 58(4): 448-462 (2009)
2008
50 Alex Ramírez, Gianfranco Bilardi, Michael Gschwind: Proceedings of the 5th Conference on Computing Frontiers, 2008, Ischia, Italy, May 5-7, 2008 ACM 2008
49EEMiquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero: MLP-Aware Dynamic Cache Partitioning. HiPEAC 2008: 337-352
48EECarmelo Acosta, Francisco J. Cazorla, Alex Ramírez, Mateo Valero: MFLUSH: Handling Long-Latency Loads in SMT On-Chip Multiprocessors. ICPP 2008: 173-181
47EEArnaldo Azevedo, Cor Meenderinck, Ben H. H. Juurlink, Mauricio Alvarez, Alex Ramírez: Analysis of video filtering on the cell processor. ISCAS 2008: 488-491
46EESebastian Isaza, Friman Sánchez, Georgi Gaydadjiev, Alex Ramírez, Mateo Valero: Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications. SAMOS 2008: 53-64
2007
45EEMiquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero: Online Prediction of Applications Cache Utility. ICSAMOS 2007: 169-177
44EEFrancisco J. Cazorla, Enrique Fernández, Peter M. W. Knijnenburg, Alex Ramírez, Rizos Sakellariou, Mateo Valero: On the Problem of Minimizing Workload Execution Time in SMT Processors. ICSAMOS 2007: 66-73
43EEDaniel Jiménez-González, Xavier Martorell, Alex Ramírez: Performance Analysis of Cell Broadband Engine for High Memory Bandwidth Applications. ISPASS 2007: 210-219
42EEMauricio Alvarez, Esther Salamí, Alex Ramírez, Mateo Valero: Performance Impact of Unaligned Memory Operations in SIMD Extensions for Video Codec Applications. ISPASS 2007: 62-71
41EEMiquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero: MLP-Aware Dynamic Cache Partitioning. PACT 2007: 418
40EEPaul Carpenter, David Ródenas, Xavier Martorell, Alex Ramírez, Eduard Ayguadé: A Streaming Machine Description and Programming Model. SAMOS 2007: 107-116
39EEMiquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero: Explaining Dynamic Cache Partitioning Speed Ups. Computer Architecture Letters 6(1): 1-4 (2007)
38EEOliverio J. Santana, Alex Ramírez, Mateo Valero: Enlarging Instruction Streams. IEEE Trans. Computers 56(10): 1342-1357 (2007)
37EEKoen De Bosschere, Wayne Luk, Xavier Martorell, Nacho Navarro, Michael F. P. O'Boyle, Dionisios N. Pnevmatikatos, Alex Ramírez, Pascal Sainrat, André Seznec, Per Stenström, Olivier Temam: High-Performance Embedded Architecture and Compilation Roadmap. T. HiPEAC 1: 5-29 (2007)
2006
36EEFriman Sánchez, Esther Salamí, Alex Ramírez, Mateo Valero: Performance Analysis of Sequence Alignment Applications. IISWC 2006: 51-60
35EEOliverio J. Santana, Ayose Falcón, Alex Ramírez, Mateo Valero: Branch predictor guided instruction decoding. PACT 2006: 202-211
34EEFrancisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero: Predictable Performance in SMT Processors: Synergy between the OS and SMTs. IEEE Trans. Computers 55(7): 785-799 (2006)
2005
33 Nader Bagherzadeh, Mateo Valero, Alex Ramírez: Proceedings of the Second Conference on Computing Frontiers, 2005, Ischia, Italy, May 4-6, 2005 ACM 2005
32EEFrancisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero: Architectural support for real-time task scheduling in SMT processors. CASES 2005: 166-176
31EECarmelo Acosta, Ayose Falcón, Alex Ramírez, Mateo Valero: A Complexity-Effective Simultaneous Multithreading Architecture. ICPP 2005: 157-164
30EEAyose Falcón, Alex Ramírez, Mateo Valero: Effective Instruction Prefetching via Fetch Prestaging. IPDPS 2005
29EEFriman Sánchez, Mauricio Alvarez, Esther Salamí, Alex Ramírez, Mateo Valero: On the Scalability of 1- and 2-Dimensional SIMD Extensions for Multimedia Applications. ISPASS 2005: 167-176
28EEAyose Falcón, Jared Stark, Alex Ramírez, Konrad K. Lai, Mateo Valero: Better Branch Prediction Through Prophet/Critic Hybrids. IEEE Micro 25(1): 80-89 (2005)
27EEAlex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero: Software Trace Cache. IEEE Trans. Computers 54(1): 22-35 (2005)
2004
26EEFrancisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero: Predictable performance in SMT processors. Conf. Computing Frontiers 2004: 433-443
25EEFrancisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero: Implicit vs. Explicit Resource Allocation in SMT Processors. DSD 2004: 44-51
24EEFrancisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero: Feasibility of QoS for SMT. Euro-Par 2004: 535-540
23EEAyose Falcón, Alex Ramírez, Mateo Valero: A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors. HPCA 2004: 244-253
22EEFrancisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández: DCache Warn: An I-Fetch Policy to Increase SMT Efficiency. IPDPS 2004
21EEAyose Falcón, Jared Stark, Alex Ramírez, Konrad Lai, Mateo Valero: Prophet/Critic Hybrid Branch Prediction. ISCA 2004: 250-263
20EEOliverio J. Santana, Alex Ramírez, Mateo Valero: Reducing Fetch Architecture Complexity Using Procedure Inlining. Interaction between Compilers and Computer Architectures 2004: 97-106
19EEFrancisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández: Dynamically Controlled Resource Allocation in SMT Processors. MICRO 2004: 171-182
18EEFrancisco J. Cazorla, Alex Ramírez, Mateo Valero, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández: QoS for High-Performance SMT Processors in Embedded Systems. IEEE Micro 24(4): 24-31 (2004)
17EEAyose Falcón, Oliverio J. Santana, Alex Ramírez, Mateo Valero: A latency-conscious SMT branch prediction architecture. IJHPCN 2(1): 11-21 (2004)
16EEFrancisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández: Optimising long-latency-load-aware fetch policies for SMT processors. IJHPCN 2(1): 45-54 (2004)
15EEOliverio J. Santana, Alex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero: A low-complexity fetch architecture for high-performance superscalar processors. TACO 1(2): 220-245 (2004)
2003
14EEFrancisco J. Cazorla, Enrique Fernández, Alex Ramírez, Mateo Valero: Improving Memory Latency Aware Fetch Policies for SMT Processors. ISHPC 2003: 70-85
13EEAyose Falcón, Oliverio J. Santana, Alex Ramírez, Mateo Valero: Tolerating Branch Predictor Latency on SMT. ISHPC 2003: 86-98
2002
12EEHans Vandierendonck, Alex Ramírez, Koenraad De Bosschere, Mateo Valero: A Comparative Study of Redundancy in Trace Caches (Research Note). Euro-Par 2002: 512-516
11EEOliverio J. Santana, Ayose Falcón, Enrique Fernández, Pedro Medina, Alex Ramírez, Mateo Valero: A Comprehensive Analysis of Indirect Branch Prediction. ISHPC 2002: 133-145
10EEAyose Falcón, Oliverio J. Santana, Pedro Medina, Enrique Fernández, Alex Ramírez, Mateo Valero: Studying New Ways for Improving Adaptive History Length Branch Predictors. ISHPC 2002: 271-280
9EEAlex Ramírez, Oliverio J. Santana, Josep-Lluis Larriba-Pey, Mateo Valero: Fetching instruction streams. MICRO 2002: 371-382
8 Alex Ramírez, Josep-Lluis Larriba-Pey, Carlos Navarro, Mateo Valero, Josep Torrellas: Software Trace Cache for Commercial Applications. International Journal of Parallel Programming 30(5): 373-395 (2002)
2001
7EEAlex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero: Branch Prediction Using Profile Data. Euro-Par 2001: 386-393
6EEAlex Ramírez, Luiz André Barroso, Kourosh Gharachorloo, Robert S. Cohn, Josep-Lluis Larriba-Pey, P. Geoffrey Lowney, Mateo Valero: Code layout optimizations for transaction processing workloads. ISCA 2001: 155-164
2000
5EECarlos Navarro, Alex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero: On the Performance of Fetch Engines Running DSS Workloads. Euro-Par 2000: 940-949
4EEAlex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero: Trace Cache Redundancy: Red & Blue Traces. HPCA 2000: 325-
3EEAlex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero: The Effect of Code Reordering on Branch Prediction. IEEE PACT 2000: 189-198
1999
2EEAlex Ramírez, Josep-Lluis Larriba-Pey, Carlos Navarro, Xavi Serrano, Mateo Valero, Josep Torrellas: Optimization of Instruction Fetch for Decision Support Workloads. ICPP 1999: 238-245
1EEAlex Ramírez, Josep-Lluis Larriba-Pey, Carlos Navarro, Josep Torrellas, Mateo Valero: Software trace cache. International Conference on Supercomputing 1999: 119-126

Coauthor Index

1Carmelo Acosta [31] [48]
2Mauricio Alvarez [29] [42] [47] [52]
3Eduard Ayguadé [40]
4Arnaldo Azevedo [47] [52]
5Nader Bagherzadeh [33]
6Luiz André Barroso [6]
7Gianfranco Bilardi [50]
8Koen De Bosschere (Koenraad De Bosschere) [12] [37]
9Paul Carpenter [40]
10Francisco J. Cazorla [14] [16] [18] [19] [22] [24] [25] [26] [32] [34] [39] [41] [44] [45] [48] [49]
11Robert S. Cohn (Robert Cohn) [6]
12Ayose Falcón [10] [11] [13] [17] [21] [23] [28] [30] [31] [35] [51]
13Enrique Fernández [10] [11] [14] [16] [18] [19] [22] [24] [25] [26] [32] [34] [44]
14Georgi Gaydadjiev (G. N. Gaydadjiev) [46]
15Kourosh Gharachorloo [6]
16Michael Gschwind [50]
17Jan Hoogerbrugge [52]
18Sebastian Isaza [46]
19Daniel Jiménez-González [43]
20Ben H. H. Juurlink [47] [52]
21Peter M. W. Knijnenburg [18] [24] [25] [26] [32] [34] [44]
22Konrad Lai (Konrad K. Lai) [21] [28]
23Josep-Lluis Larriba-Pey [1] [2] [3] [4] [5] [6] [7] [8] [9] [15] [27]
24P. Geoffrey Lowney [6]
25Wayne Luk [37]
26Xavier Martorell [37] [40] [43]
27Pedro Medina [10] [11]
28Cor Meenderinck [47] [52]
29Miquel Moretó [39] [41] [45] [49]
30Carlos Navarro [1] [2] [5] [8]
31Nacho Navarro [37]
32Michael F. P. O'Boyle [37]
33Dionisios N. Pnevmatikatos [37]
34David Ródenas [40]
35Pascal Sainrat [37]
36Rizos Sakellariou [18] [24] [25] [26] [32] [34] [44]
37Esther Salamí [29] [36] [42]
38Friman Sánchez [29] [36] [46]
39Oliverio J. Santana [9] [10] [11] [13] [15] [17] [20] [35] [38] [51]
40Xavi Serrano [2]
41André Seznec [37]
42Jared Stark [21] [28]
43Per Stenström [37]
44Olivier Temam [37]
45Andrei Terechko [52]
46Josep Torrellas [1] [2] [8]
47Mateo Valero [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] [33] [34] [35] [36] [38] [39] [41] [42] [44] [45] [46] [48] [49] [51]
48Hans Vandierendonck [12]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)