| 2008 |
|---|
| 11 | EE | Miquel Pericàs,
Eduard Ayguadé,
Javier Zalamea,
Josep Llosa,
Mateo Valero:
Power-efficient VLIW design using clustering and widening.
IJES 3(3): 141-149 (2008) |
| 2004 |
|---|
| 10 | EE | Miquel Pericàs,
Eduard Ayguadé,
Javier Zalamea,
Josep Llosa,
Mateo Valero:
with Wide Functional Units.
SAMOS 2004: 88-97 |
| 9 | EE | Javier Zalamea,
Josep Llosa,
Eduard Ayguadé,
Mateo Valero:
Register Constrained Modulo Scheduling.
IEEE Trans. Parallel Distrib. Syst. 15(5): 417-430 (2004) |
| 8 | EE | Miquel Pericàs,
Eduard Ayguadé,
Javier Zalamea,
Josep Llosa,
Mateo Valero:
High-performance and low-power VLIW cores for numerical computations.
IJHPCN 1(4): 171-179 (2004) |
| 7 | EE | Javier Zalamea,
Josep Llosa,
Eduard Ayguadé,
Mateo Valero:
Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures.
International Journal of Parallel Programming 32(6): 447-474 (2004) |
| 2003 |
|---|
| 6 | EE | Javier Zalamea,
Josep Llosa,
Eduard Ayguadé,
Mateo Valero:
Hierarchical Clustered Register File Organization for VLIW Processors.
IPDPS 2003: 77 |
| 5 | EE | Miquel Pericàs,
Eduard Ayguadé,
Javier Zalamea,
Josep Llosa,
Mateo Valero:
Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes.
ISHPC 2003: 113-126 |
| 2001 |
|---|
| 4 | EE | Javier Zalamea,
Josep Llosa,
Eduard Ayguadé,
Mateo Valero:
MIRS: Modulo Scheduling with Integrated Register Spilling.
LCPC 2001: 239-253 |
| 3 | EE | Javier Zalamea,
Josep Llosa,
Eduard Ayguadé,
Mateo Valero:
Modulo scheduling with integrated register spilling for clustered VLIW architectures.
MICRO 2001: 160-169 |
| 2000 |
|---|
| 2 | EE | Javier Zalamea,
Josep Llosa,
Eduard Ayguadé,
Mateo Valero:
Two-level hierarchical register file organization for VLIW processors.
MICRO 2000: 137-146 |
| 1 | EE | Javier Zalamea,
Josep Llosa,
Eduard Ayguadé,
Mateo Valero:
Improved spill code generation for software pipelined loops.
PLDI 2000: 134-144 |
