Oliverio J. Santana

2009
18	EE	Oliverio J. Santana, Ayose Falcón, Alex Ramírez, Mateo Valero: DIA: A Complexity-Effective Decoding Architecture. IEEE Trans. Computers 58(4): 448-462 (2009)
2008
17	EE	Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero: Runahead Threads to improve SMT performance. HPCA 2008: 149-158
16	EE	Alejandro García, Oliverio J. Santana, Enrique Fernández, Pedro Medina, Mateo Valero: LPA: A First Approach to the Loop Processor Architecture. HiPEAC 2008: 273-287
2007
15	EE	Javier Vera, Francisco J. Cazorla, Alex Pajuelo, Oliverio J. Santana, Enrique Fernández, Mateo Valero: FAME: FAirly MEasuring Multithreaded Architectures. PACT 2007: 305-316
14	EE	Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero: Runahead Threads: Reducing Resource Contention in SMT Processors. PACT 2007: 423
13	EE	Oliverio J. Santana, Alex Ramírez, Mateo Valero: Enlarging Instruction Streams. IEEE Trans. Computers 56(10): 1342-1357 (2007)
2006
12	EE	Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero: Kilo-instruction processors, runahead and prefetching. Conf. Computing Frontiers 2006: 269-278
11	EE	Oliverio J. Santana, Ayose Falcón, Alex Ramírez, Mateo Valero: Branch predictor guided instruction decoding. PACT 2006: 202-211
2005
10	EE	Adrián Cristal, Oliverio J. Santana, Francisco J. Cazorla, Marco Galluzzi, Tanausú Ramírez, Miquel Pericàs, Mateo Valero: Kilo-Instruction Processors: Overcoming the Memory Wall. IEEE Micro 25(3): 48-57 (2005)
2004
9	EE	Adrián Cristal, Oliverio J. Santana, Mateo Valero: Maintaining Thousands of In-flight Instructions. Euro-Par 2004: 9-20
8	EE	Oliverio J. Santana, Alex Ramírez, Mateo Valero: Reducing Fetch Architecture Complexity Using Procedure Inlining. Interaction between Compilers and Computer Architectures 2004: 97-106
7	EE	Ayose Falcón, Oliverio J. Santana, Alex Ramírez, Mateo Valero: A latency-conscious SMT branch prediction architecture. IJHPCN 2(1): 11-21 (2004)
6	EE	Oliverio J. Santana, Alex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero: A low-complexity fetch architecture for high-performance superscalar processors. TACO 1(2): 220-245 (2004)
5	EE	Adrián Cristal, Oliverio J. Santana, Mateo Valero, José F. Martínez: Toward kilo-instruction processors. TACO 1(4): 389-417 (2004)
2003
4	EE	Ayose Falcón, Oliverio J. Santana, Alex Ramírez, Mateo Valero: Tolerating Branch Predictor Latency on SMT. ISHPC 2003: 86-98
2002
3	EE	Oliverio J. Santana, Ayose Falcón, Enrique Fernández, Pedro Medina, Alex Ramírez, Mateo Valero: A Comprehensive Analysis of Indirect Branch Prediction. ISHPC 2002: 133-145
2	EE	Ayose Falcón, Oliverio J. Santana, Pedro Medina, Enrique Fernández, Alex Ramírez, Mateo Valero: Studying New Ways for Improving Adaptive History Length Branch Predictors. ISHPC 2002: 271-280
1	EE	Alex Ramírez, Oliverio J. Santana, Josep-Lluis Larriba-Pey, Mateo Valero: Fetching instruction streams. MICRO 2002: 371-382

Coauthor Index

1	Francisco J. Cazorla	[10] [15]
2	Adrián Cristal	[5] [9] [10]
3	Ayose Falcón	[2] [3] [4] [7] [11] [18]
4	Enrique Fernández	[2] [3] [15] [16]
5	Marco Galluzzi	[10]
6	Alejandro García	[16]
7	Josep-Lluis Larriba-Pey	[1] [6]
8	José F. Martínez	[5]
9	Pedro Medina	[2] [3] [16]
10	Alex Pajuelo	[12] [14] [15] [17]
11	Miquel Pericàs	[10]
12	Alex Ramírez	[1] [2] [3] [4] [6] [7] [8] [11] [13] [18]
13	Tanausú Ramírez	[10] [12] [14] [17]
14	Mateo Valero	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18]
15	Javier Vera	[15]