2008 | ||
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34 | EE | Larry Seiler, Doug Carmean, Eric Sprangle, Tom Forsyth, Michael Abrash, Pradeep Dubey, Stephen Junkins, Adam Lake, Jeremy Sugerman, Robert Cavin, Roger Espasa, Ed Grochowski, Toni Juan, Pat Hanrahan: Larrabee: a many-core x86 architecture for visual computing. ACM Trans. Graph. 27(3): (2008) |
2006 | ||
33 | EE | Jordi Roca, Victor Moya Del Barrio, Carlos González, Chema Solis, Agustin Fernández, Roger Espasa: Workload Characterization of 3D Games. IISWC 2006: 17-26 |
32 | EE | Victor Moya Del Barrio, Carlos González, Jordi Roca, Agustin Fernández, Roger Espasa: ATTILA: a cycle-level execution-driven simulator for modern GPU architectures. ISPASS 2006: 231-241 |
2005 | ||
31 | EE | Victor Moya Del Barrio, Carlos González, Jordi Roca, Agustin Fernández, Roger Espasa: A Single (Unified) Shader GPU Microarchitecture for Embedded Systems. HiPEAC 2005: 286-301 |
30 | EE | Victor Moya Del Barrio, Carlos González, Jordi Roca, Agustin Fernández, Roger Espasa: Shader Performance Analysis on a Modern GPU Architecture. MICRO 2005: 355-364 |
29 | EE | André Seznec, Roger Espasa: Conflict-Free Accesses to Strided Vectors on a Banked Cache. IEEE Trans. Computers 54(7): 913-196 (2005) |
2004 | ||
28 | EE | Manel Fernández, Roger Espasa: Link-Time Path-Sensitive Memory Redundancy Elimination. HPCA 2004: 300-310 |
27 | EE | Manel Fernández, Roger Espasa: Link-Time Optimization Techniques for Eliminating Conditional Branch Redundancies. Interaction between Compilers and Computer Architectures 2004: 87-96 |
2003 | ||
26 | EE | Manel Fernández, Roger Espasa, Saumya K. Debray: Load redundancy elimination on executable code. Concurrency and Computation: Practice and Experience 15(10): 979-997 (2003) |
25 | EE | Francisca Quintana, Jesús Corbal, Roger Espasa, Mateo Valero: A Cost-Effective Architecture for Vectorizable Numerical and Multimedia Applications. Theory Comput. Syst. 36(5): 575-593 (2003) |
2002 | ||
24 | EE | Manel Fernández, Roger Espasa: Speculative Alias Analysis for Executable Code. IEEE PACT 2002: 222-231 |
23 | EE | Roger Espasa, Federico Ardanaz, Julio Gago, Roger Gramunt, Isaac Hernandez, Toni Juan, Joel S. Emer, Stephen Felix, P. Geoffrey Lowney, Matthew Mattina, André Seznec: Tarantula: A Vector Extension to the Alpha Architecture. ISCA 2002: 281- |
22 | EE | Jesús Corbal, Roger Espasa, Mateo Valero: Three-dimensional memory vectorization for high bandwidth media memory systems. MICRO 2002: 149-160 |
21 | EE | Joel S. Emer, Pritpal Ahuja, Eric Borch, Artur Klauser, Chi-Keung Luk, Srilatha Manne, Shubhendu S. Mukherjee, Harish Patil, Steven Wallace, Nathan L. Binkert, Roger Espasa, Toni Juan: Asim: A Performance Model Framework. IEEE Computer 35(2): 68-76 (2002) |
2001 | ||
20 | EE | Manel Fernández, Roger Espasa, Saumya K. Debray: Load Redundancy Elimination on Executable Code. Euro-Par 2001: 221-229 |
19 | EE | Eduard Ayguadé, Fredrik Dahlgren, Christine Eisenbeis, Roger Espasa, Guang R. Gao, Henk L. Muller, Rizos Sakellariou, André Seznec: Topic 08+13: Instruction-Level Parallelism and Computer Architecture. Euro-Par 2001: 385 |
18 | EE | Jesús Corbal, Roger Espasa, Mateo Valero: DLP + TLP Processors for the Next Generation of Media Workloads. HPCA 2001: 219-228 |
17 | EE | Jesús Corbal, Roger Espasa, Mateo Valero: On the Efficiency of Reductions in µ-SIMD Media Extensions. IEEE PACT 2001: 83- |
16 | EE | Francisca Quintana, Jesús Corbal, Roger Espasa, Mateo Valero: A cost effective architecture for vectorizable numerical and multimedia applications. SPAA 2001: 103-112 |
1999 | ||
15 | EE | Francisca Quintana, Jesús Corbal, Roger Espasa, Mateo Valero: Adding a vector unit to a superscalar processor. International Conference on Supercomputing 1999: 1-10 |
14 | EE | Jesús Corbal, Roger Espasa, Mateo Valero: Exploiting a New Level of DLP in Multimedia Applications. MICRO 1999: 72- |
13 | EE | Roger Espasa, Mateo Valero: A Simulation Study of Decoupled Vector Architectures. The Journal of Supercomputing 14(2): 124-152 (1999) |
1998 | ||
12 | EE | Jesús Corbal, Roger Espasa, Mateo Valero: Command Vector Memory Systems: High Performance at Low Cost. IEEE PACT 1998: 68- |
11 | EE | Luis Villa, Roger Espasa, Mateo Valero: A Performance Study of Out-of-order Vector Architectures and Short Registers. International Conference on Supercomputing 1998: 37-44 |
10 | EE | Roger Espasa, Mateo Valero, James E. Smith: Vector Architectures: Past, Present and Future. International Conference on Supercomputing 1998: 425-432 |
9 | EE | Alexandre Farcy, Olivier Temam, Roger Espasa, Toni Juan: Dataflow Analysis of Branch Mispredictions and Its Application to Early Resolution of Branch Outcomes. MICRO 1998: 59-68 |
8 | Luis Villa, Roger Espasa, Mateo Valero: Registers Size Influence on Vector Architectures. VECPAR 1998: 439-451 | |
7 | Francisca Quintana, Roger Espasa, Mateo Valero: An ISA Comparison Between Superscalar and Vector Processors. VECPAR 1998: 548-560 | |
1997 | ||
6 | EE | Roger Espasa, Mateo Valero: Multithreaded Vector Architectures. HPCA 1997: 237- |
5 | EE | Luis Villa, Roger Espasa, Mateo Valero: Effective Usage of Vector Registers in Advanced Vector Architectures. IEEE PACT 1997: 250-260 |
4 | EE | Roger Espasa, Mateo Valero: A Victim Cache for Vector Registers. International Conference on Supercomputing 1997: 293-300 |
3 | EE | Roger Espasa, Mateo Valero, James E. Smith: Out-of-Order Vector Architectures. MICRO 1997: 160-170 |
1996 | ||
2 | EE | Roger Espasa, Mateo Valero: Decoupled Vector Architectures. HPCA 1996: 281-290 |
1995 | ||
1 | EE | Roger Espasa, Mateo Valero, David A. Padua, Marta Jiménez, Eduard Ayguadé: Quantitative analysis of vector code. PDP 1995: 452-463 |