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Sriram Vajapeyam

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2002
15EESiddhartha V. Tambat, Sriram Vajapeyam: Page-Level Behavior of Cache Contention. Computer Architecture Letters 1: (2002)
2001
14 Burkhard Monien, Viktor K. Prasanna, Sriram Vajapeyam: High Performance Computing - HiPC 2001, 8th International Conference, Hyderabad, India, December, 17-20, 2001, Proceedings Springer 2001
13EESriram Vajapeyam, Mateo Valero: Early 21st Century Processors - Guest Editors' Introduction. IEEE Computer 34(4): 47-50 (2001)
2000
12 Mateo Valero, Viktor K. Prasanna, Sriram Vajapeyam: High Performance Computing - HiPC 2000, 7th International Conference, Bangalore, India, December 17-20, 2000, Proceedings Springer 2000
11EESiddhartha V. Tambat, Sriram Vajapeyam: Non-Strict Cache Coherence: Exploiting Data-Race Tolerance in Emerging Applications. ICPP 2000: 87-94
1999
10 Sriram Vajapeyam: Whither Indian Computer Science R & D? HiPC 1999: 175
9EESriram Vajapeyam, P. J. Joseph, Tulika Mitra: Dynamic Vectorization: A Mechanism for Exploiting Far-Flung ILP in Ordinary Programs. ISCA 1999: 16-27
1998
8EEGurindar S. Sohi, Sriram Vajapeyam: Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors. 25 Years ISCA: Retrospectives and Reprints 1998: 329-336
1997
7EESriram Vajapeyam, Tulika Mitra: Improving Superscalar Instruction Dispatch and Issue by Exploiting Dynamic Code Sequences. ISCA 1997: 1-12
6 James E. Smith, Sriram Vajapeyam: Trace Processors: Moving to Fourth-Generation Microarchitectures. IEEE Computer 30(9): 68-74 (1997)
1993
5 Sriram Vajapeyam, Wei-Chung Hsu: Toward Effective Scalar Hardware for Highly Vectorizable Applications. J. Parallel Distrib. Comput. 19(3): 147-162 (1993)
1992
4EESriram Vajapeyam, Wei-Chung Hsu: On the instruction-level characteristics of scalar code in highly-vectorized scientific applications. MICRO 1992: 20-28
1991
3EESriram Vajapeyam, Gurindar S. Sohi, Wei-Chung Hsu: An Empirical Study of the CRAY Y-MP Processor Using the Perfect Club Benchmarks. ISCA 1991: 170-179
1989
2 Gurindar S. Sohi, Sriram Vajapeyam: Tradeoffs in Instruction Format Design for Horizontal Architectures. ASPLOS 1989: 15-25
1987
1 Gurindar S. Sohi, Sriram Vajapeyam: Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors. ISCA 1987: 27-34

Coauthor Index

1Wei-Chung Hsu [3] [4] [5]
2P. J. Joseph [9]
3Tulika Mitra [7] [9]
4Burkhard Monien [14]
5Viktor K. Prasanna (V. K. Prasanna Kumar) [12] [14]
6James E. Smith [6]
7Gurindar S. Sohi [1] [2] [3] [8]
8Siddhartha V. Tambat [11] [15]
9Mateo Valero [12] [13]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)