Robert Cohn
List of publications from the DBLP Bibliography Server - FAQ
2007 | ||
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18 | EE | Vijay Janapa Reddi, Dan Connors, Robert Cohn, Michael D. Smith: Persistent Code Caching: Exploiting Code Reuse Across Executions and Applications. CGO 2007: 74-88 |
17 | EE | Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, Robert Cohn: VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization. ISCA 2007: 424-435 |
2006 | ||
16 | EE | Kim M. Hazelwood, Robert S. Cohn: A Cross-Architectural Interface for Code Cache Manipulation. CGO 2006: 17-27 |
15 | EE | Satish Narayanasamy, Cristiano Pereira, Harish Patil, Robert Cohn, Brad Calder: Automatic logging of operating system effects to guide application-level architecture simulation. SIGMETRICS/Performance 2006: 216-227 |
2005 | ||
14 | EE | Chi-Keung Luk, Robert S. Cohn, Robert Muth, Harish Patil, Artur Klauser, P. Geoffrey Lowney, Steven Wallace, Vijay Janapa Reddi, Kim M. Hazelwood: Pin: building customized program analysis tools with dynamic instrumentation. PLDI 2005: 190-200 |
2004 | ||
13 | EE | Chi-Keung Luk, Robert Muth, Harish Patil, Robert S. Cohn, P. Geoffrey Lowney: Ispike: A Post-link Optimizer for the Intel®Itanium®Architecture. CGO 2004: 15-26 |
12 | EE | Harish Patil, Robert S. Cohn, Mark Charney, Rajiv Kapoor, Andrew Sun, Anand Karunanidhi: Pinpointing Representative Portions of Large Intel® Itanium® Programs with Dynamic Instrumentation. MICRO 2004: 81-92 |
2002 | ||
11 | EE | Chi-Keung Luk, Robert Muth, Harish Patil, Richard Weiss, P. Geoffrey Lowney, Robert S. Cohn: Profile-guided post-link stride prefetching. ICS 2002: 167-178 |
2001 | ||
10 | EE | Alex Ramírez, Luiz André Barroso, Kourosh Gharachorloo, Robert S. Cohn, Josep-Lluis Larriba-Pey, P. Geoffrey Lowney, Mateo Valero: Code layout optimizations for transaction processing workloads. ISCA 2001: 155-164 |
2000 | ||
9 | EE | Robert S. Cohn, P. Geoffrey Lowney: Design and Analysis of Profile-Based Optimization in Compaq's Compilation Tools for Alpha. J. Instruction-Level Parallelism 2: (2000) |
1998 | ||
8 | EE | Robert S. Cohn, David W. Goodwin, P. Geoffrey Lowney: Optimizing Alpha Executables on Windows NT with Spike. Digital Technical Journal 9(4): (1998) |
1996 | ||
7 | EE | Robert S. Cohn, P. Geoffrey Lowney: Hot Cold Optimization of Large Windows/NT Applications. MICRO 1996: 80-89 |
1991 | ||
6 | Robert Cohn: Source Level Debugging of Automatically Parallelized Code. Workshop on Parallel and Distributed Debugging 1991: 132-143 | |
1990 | ||
5 | Shekhar Borkar, Robert Cohn, George W. Cox, Thomas R. Gross, H. T. Kung, Monica S. Lam, Margie Levine, Brian Moore, Wire Moore, Craig Peterson, Jim Susman, Jim Sutton, John Urbanski, Jon A. Webb: Supporting Systolic and Memory Communciation in iWarp. ISCA 1990: 70-81 | |
1989 | ||
4 | Robert Cohn, Thomas R. Gross, Monica S. Lam, P. S. Tseng: Architecture and Compiler Tradeoffs for a Long Instruction Word Microprocessor. ASPLOS 1989: 2-14 | |
1988 | ||
3 | EE | Shekhar Borkar, Robert Cohn, George W. Cox, Sha Gleason, Thomas R. Gross: Warp: an integrated solution of high-speed parallel computing. SC 1988: 330-339 |
1987 | ||
2 | Marco Annaratone, Emmanuel A. Arnould, Robert Cohn, Thomas R. Gross, H. T. Kung, Monica S. Lam, Onat Menzilcioglu, Ken Sarocky, John Senko, Jon A. Webb: Architecture of Warp. COMPCON 1987: 264-267 | |
1 | Bernd Bruegge, Chang-Hsin Chang, Robert Cohn, Thomas R. Gross, Monica S. Lam, Peter Lieu, Abu Noaman, David Yam: Programming Warp. COMPCON 1987: 268-271 |