3. WMPI 2004: Munich, Germany

• Magnus Ekman, Per Stenström:
  A case for multi-level main memory. 1-8
  Electronic Edition (ACM DL) BibTeX
• Erik G. Hallnor, Steven K. Reinhardt:
  A compressed memory hierarchy using an indirect index cache. 9-15
  Electronic Edition (ACM DL) BibTeX
• Jay B. Brockman, Shyamkumar Thoziyoor, Shannon K. Kuntz, Peter M. Kogge:
  A low cost, multithreaded processing-in-memory system. 16-22
  Electronic Edition (ACM DL) BibTeX
• Collin McCurdy, Charles N. Fischer:
  A localizing directory coherence protocol. 23-29
  Electronic Edition (ACM DL) BibTeX
• Faye A. Briggs, Suresh Chittor, Kai Cheng:
  Micro-architecture techniques in the intel E8870 scalable memory controller. 30-36
  Electronic Edition (ACM DL) BibTeX
• Stephen Somogyi, Thomas F. Wenisch, Nikolaos Hardavellas, Jangwoo Kim, Anastassia Ailamaki, Babak Falsafi:
  Memory coherence activity prediction in commercial workloads. 37-45
  Electronic Edition (ACM DL) BibTeX
• José González, Fernando Latorre, Antonio González:
  Cache organizations for clustered microarchitectures. 46-55
  Electronic Edition (ACM DL) BibTeX
• Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt:
  Understanding the effects of wrong-path memory references on processor performance. 56-64
  Electronic Edition (ACM DL) BibTeX
• Muhamed F. Mudawar:
  Scalable cache memory design for large-scale SMT architectures. 65-71
  Electronic Edition (ACM DL) BibTeX
• Marco Galluzzi, Ramón Beivide, Valentin Puente, José-Ángel Gregorio, Adrián Cristal, Mateo Valero:
  Evaluating kilo-instruction multiprocessors. 72-79
  Electronic Edition (ACM DL) BibTeX
• Chitra Natarajan, Bruce Christenson, Faye A. Briggs:
  A study of performance impact of memory controller features in multi-processor server environment. 80-87
  Electronic Edition (ACM DL) BibTeX
• G. Surendra, Subhasis Banerjee, S. K. Nandy:
  On the effectiveness of prefetching and reuse in reducing L1 data cache traffic: a case study of Snort. 88-95
  Electronic Edition (ACM DL) BibTeX
• Doron Nakar, Shlomo Weiss:
  Selective main memory compression by identifying program phase changes. 96-101
  Electronic Edition (ACM DL) BibTeX
• Wolfgang Raab, Hans-Martin Blüthgen, Ulrich Ramacher:
  A low-power memory hierarchy for a fully programmable baseband processor. 102-106
  Electronic Edition (ACM DL) BibTeX
• Irina Chihaia, Thomas R. Gross:
  An analytical model for software-only main memory compression. 107-113
  Electronic Edition (ACM DL) BibTeX
• Lars Wehmeyer, Urs Helmig, Peter Marwedel:
  Compiler-optimized usage of partitioned memories. 114-120
  Electronic Edition (ACM DL) BibTeX
• Chikafumi Takahashi, Masaaki Kondo, Taisuke Boku, Daisuke Takahashi, Hiroshi Nakamura, Mitsuhisa Sato:
  SCIMA-SMP: on-chip memory processor architecture for SMP. 121-128
  Electronic Edition (ACM DL) BibTeX
• Ramesh V. Peri, John Fernando, Ravi Kolagotla:
  Addressing mode driven low power data caches for embedded processors. 129-135
  Electronic Edition (ACM DL) BibTeX
• Steven T. Gabriel, David S. Wise:
  The Opie compiler from row-major source to Morton-ordered matrices. 136-144
  Electronic Edition (ACM DL) BibTeX