HiPEAC 2008: Göteborg, Sweden

Invited Program

• Mateo Valero, Jesús Labarta:
  Supercomputing for the Future, Supercomputing from the Past (Keynote). 3-5
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Multithreaded and Multicore Processors

• Kevin D. Kissell:
  MIPS MT: A Multithreaded RISC Architecture for Embedded Real-Time Processing. 9-21
  Electronic Edition (link) BibTeX
• James Psota, Anant Agarwal:
  rMPI: Message Passing on Multicore Processors with On-Chip Interconnect. 22-37
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• Filip Blagojevic, Xizhou Feng, Kirk W. Cameron, Dimitrios S. Nikolopoulos:
  Modeling Multigrain Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE. 38-52
  Electronic Edition (link) BibTeX

Reconfigurable - ASIP

• Ricardo Chaves, Blagomir Donchev, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis:
  BRAM-LUT Tradeoff on a Polymorphic DES Design. 55-65
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• Frank Bouwens, Mladen Berekovic, Bjorn De Sutter, Georgi Gaydadjiev:
  Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array. 66-81
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• Jochem Govers, Jos Huisken, Mladen Berekovic, Olivier Rousseaux, Frank Bouwens, Michael De Nil, Jef L. van Meerbergen:
  Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP. 82-96
  Electronic Edition (link) BibTeX

Compiler Optimizations

• Tzi-cker Chiueh:
  Fast Bounds Checking Using Debug Register. 99-113
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• Stijn Eyerman, Lieven Eeckhout, James E. Smith:
  Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis. 114-129
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• Marco Cornero, Roberto Costa, Ricardo Fernández Pascual, Andrea C. Ornstein, Erven Rohou:
  An Experimental Environment Validating the Suitability of CLI as an Effective Deployment Format for Embedded Systems. 130-144
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Industrial Processors and Application Parallelization

• Todd T. Hahn, Eric Stotzer, Dineel Sule, Mike Asal:
  Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions. 147-160
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• Hans Vandierendonck, Sean Rul, Michiel Questier, Koen De Bosschere:
  Experiences with Parallelizing a Bio-informatics Program on the Cell BE. 161-175
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• Harald Servat, Cecilia González-Alvarez, Xavier Aguilar, Daniel Cabrera-Benitez, Daniel Jiménez-González:
  Drug Design Issues on the Cell BE. 176-190
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Power-Aware Techniques

• Praveen Raghavan, Andy Lambrechts, Javed Absar, Murali Jayapala, Francky Catthoor, Diederik Verkest:
  Coffee: COmpiler Framework for Energy-Aware Exploration. 193-208
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• Nevine AbouGhazaleh, Bruce R. Childers, Daniel Mossé, Rami G. Melhem:
  Integrated CPU Cache Power Management in Multiple Clock Domain Processors. 209-223
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• Maziar Goudarzi, Tohru Ishihara, Hamid Noori:
  Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation. 224-239
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High-Performance Processors

• Yiannakis Sazeides, Andreas Moustakas, Kypros Constantinides, Marios Kleanthous:
  The Significance of Affectors and Affectees Correlations for Branch Prediction. 243-257
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• Patrick Akl, Andreas Moshovos:
  Turbo-ROB: A Low Cost Checkpoint/Restore Accelerator. 258-272
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• Alejandro García, Oliverio J. Santana, Enrique Fernández, Pedro Medina, Mateo Valero:
  LPA: A First Approach to the Loop Processor Architecture. 273-287
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Profiles: Collection and Analysis

• Roy Levin, Ilan Newman, Gadi Haber:
  Complementing Missing and Inaccurate Profiling Using a Minimum Cost Circulation Algorithm. 291-304
  Electronic Edition (link) BibTeX
• Vincent M. Weaver, Sally A. McKee:
  Using Dynamic Binary Instrumentation to Generate Multi-platform SimPoints: Methodology and Accuracy. 305-319
  Electronic Edition (link) BibTeX
• Frederik Vandeputte, Lieven Eeckhout:
  Phase Complexity Surfaces: Characterizing Time-Varying Program Behavior. 320-334
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Optimizing Memory Performance

• Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero:
  MLP-Aware Dynamic Cache Partitioning. 337-352
  Electronic Edition (link) BibTeX
• Subhradyuti Sarkar, Dean M. Tullsen:
  Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture. 353-368
  Electronic Edition (link) BibTeX
• Chun-Chieh Lin, Chuen-Liang Chen:
  Code Arrangement of Embedded Java Virtual Machine for NAND Flash Memory. 369-383
  Electronic Edition (link) BibTeX
• Yosi Ben-Asher, Omer Boehm, Daniel Citron, Gadi Haber, Moshe Klausner, Roy Levin, Yousef Shajrawi:
  Aggressive Function Inlining: Preventing Loop Blockings in the Instruction Cache. 384-397
  Electronic Edition (link) BibTeX