Víctor Viñals

2008
18	EE	Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals: Low-Cost Adaptive Data Prefetching. Euro-Par 2008: 327-336
2007
17	EE	Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo Valero: Microarchitectural Support for Speculative Register Renaming. IPDPS 2007: 1-10
2006
16	EE	Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo Valero: Speculative early register release. Conf. Computing Frontiers 2006: 291-302
15	EE	A. de Dios, B. Sahelices, Pablo Ibáñez, Víctor Viñals, José M. Llabería: Speeding-Up Synchronizations in DSM Multiprocessors. Euro-Par 2006: 473-484
14	EE	Jesús Alastruey, José Luis Briz, Pablo Ibáñez, Víctor Viñals: Software Demand, Hardware Supply. IEEE Micro 26(4): 72-82 (2006)
2005
13	EE	Enrique F. Torres, Pablo Ibáñez, Víctor Viñals, José María Llabería: Store Buffer Design in First-Level Multibanked Data Caches. ISCA 2005: 469-480
12	EE	Teresa Monreal, Víctor Viñals, Antonio González, Mateo Valero: Hardware support for early register release. IJHPCN 3(2/3): 83-94 (2005)
11	EE	María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas: Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors. TACO 2(3): 247-279 (2005)
2004
10	EE	Enrique F. Torres, Pablo Ibáñez, Víctor Viñals, José María Llabería: Contents Management in First-Level Multibanked Data Caches. Euro-Par 2004: 516-524
9	EE	Teresa Monreal, Víctor Viñals, José González, Antonio González, Mateo Valero: Late Allocation and Early Release of Physical Registers. IEEE Trans. Computers 53(10): 1244-1259 (2004)
2003
8	EE	Enrique F. Torres, Pablo Ibáñez, Víctor Viñals, José María Llabería: Counteracting Bank Misprediction in Sliced First-Level Caches. Euro-Par 2003: 586-596
7	EE	María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas: Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors. HPCA 2003: 191-202
6	EE	María Jesús Garzarán, Milos Prvulovic, Víctor Viñals, José María Llabería, Lawrence Rauchwerger, Josep Torrellas: Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation. IEEE PACT 2003: 170-
2002
5	EE	Teresa Monreal, Víctor Viñals, Antonio González, Mateo Valero: Hardware Schemes for Early Register Release. ICPP 2002: 5-13
2000
4	EE	Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals: Dynamic Register Renaming Through Virtual-Physical Registers. J. Instruction-Level Parallelism 2: (2000)
1999
3	EE	Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals: Delaying Physical Register Allocation through Virtual-Physical Registers. MICRO 1999: 186-
1998
2	EE	Pablo Ibáñez, Víctor Viñals, José Luis Briz, María Jesús Garzarán: Characterization and Improvement of Load/Store Cache-based Prefetching. International Conference on Supercomputing 1998: 369-376
1996
1	EE	Pablo Ibáñez, Víctor Viñals: Performance Assessment of Contents Management in Multilevel On-Chip Caches. EUROMICRO 1996: 431-440

Coauthor Index

1	Jesús Alastruey	[14] [16] [17]
2	José Luis Briz	[2] [14] [18]
3	A. de Dios	[15]
4	María Jesús Garzarán	[2] [6] [7] [11]
5	Antonio González	[3] [4] [5] [9] [12]
6	José González	[3] [4] [9]
7	Pablo Ibáñez	[1] [2] [8] [10] [13] [14] [15]
8	Pablo E. Ibáñez	[18]
9	José María Llabería (José M. Llabería)	[6] [7] [8] [10] [11] [13] [15]
10	Teresa Monreal	[3] [4] [5] [9] [12] [16] [17]
11	Milos Prvulovic	[6] [7] [11]
12	Luis M. Ramos	[18]
13	Lawrence Rauchwerger	[6] [7] [11]
14	B. Sahelices	[15]
15	Josep Torrellas	[6] [7] [11]
16	Enrique F. Torres	[8] [10] [13]
17	Mateo Valero	[3] [4] [5] [9] [12] [16] [17]