2. HPCA 1996: San Jose, CA, USA

Proceedings of the Second International Symposium on High-Performance Computer Architecture, February 3-7, 1996, San Jose, CA, USA. IEEE Computer Society, ISBN 0-8186-7237-4, online publication: http://computer.org/proceedings/hpca/7237/7237toc.htm

Network of Workstations

Magnus Karlsson, Per Stenström:
Performance Evaluation of a Cluster-Based Multiprocessor Built from ATM Switches and Bus-Based Multiprocessor Servers. 4-13
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Liviu Iftode, Cezary Dubnicki, Edward W. Felten, Kai Li:
Improving Release-Consistent Shared Virtual Memory Using Automatic Update. 14-25
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Sarita V. Adve, Alan L. Cox, Sandhya Dwarkadas, Ramakrishnan Rajamony, Willy Zwaenepoel:
A Comparison of Entry Consistency and Lazy Release Consistency Implementations. 26-37
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Instruction Scheduling

Keith I. Farkas, Norman P. Jouppi, Paul Chow:
Register File Design Considerations in Dynamically Scheduled Processors. 40-51
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Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao:
Co-Scheduling Hardware and Software Pipelines. 52-61
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Vijay S. Iyengar, Louise Trevillyan, Pradip Bose:
Representative Traces for Processor Models with Infinite Cache. 62-72
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Shared-Memory Multiprocessors

Basem A. Nayfeh, Kunle Olukotun, Jaswinder Pal Singh:
The Impact of Shared-Cache Clustering in Small-Scale Shared-Memory Multiprocessors. 74-84
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Chun Xia, Josep Torrellas:
Improving the Data Cache Performance of Multiprocessor Operating Systems. 85-94
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Anders Landin, Fredrik Dahlgren:
Bus-Based COMA - Reducing Traffic in Shared-Bus Multiprocessors. 95-105
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Interconnection Networks

Hossam A. ElGindy, Arun K. Somani, Heiko Schröder, Hartmut Schmeck, Andrew Spray:
RMB - A Reconfigurable Multiple Bus Network. 108-117
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Chunming Qiao, Yousong Mei:
On the Multiplexing Degree Required to Embed Permutations in a Class of Networks with Direct Interconnects. 118-129
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Guihai Chen, Francis C. M. Lau:
Shuffle-Ring: Overcoming the Increasing Degree of Hypercube. 130-138
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Network Interfaces

Evangelos P. Markatos, Manolis Katevenis:
Telegraphos: High-Performance Networking for Parallel Processing on Workstation Clusters. 144-153
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Matthias A. Blumrich, Cezary Dubnicki, Edward W. Felten, Kai Li:
Protected, User-Level DMA for the SHRIMP Network Interface. 154-165
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Leonidas I. Kontothanassis, Michael L. Scott:
Using Memory-Mapped Network Interfaces to Improve the Performance of Distributed Shared Memory. 166-177
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Network Routing

Ran Libeskind-Hadas, Kevin Watkins, Thomas Hehre:
Fault-Tolerant Multicast Routing in the Mesh with No Virtual Channels. 180-190
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Hyunmin Park, Dharma P. Agrawal:
A Topology-Independent Generic Methodology for Deadlock-Free Wormhole Routing. 191-200
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Suresh Chalasani, Rajendra V. Boppana:
Fault-Tolerance with Multimodule Routers. 201-210
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Multiprocessor Systems

Henk L. Muller, Paul W. A. Stallard, David H. D. Warren:
Multitasking and Multithreading on a Multiprocessor with Virtual Shared Memory. 212-221
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John A. Reisner, Tom S. Wailes:
A Cache Coherency Protocol for Optically Connected Parallel Computer Systems. 222-231
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Wen-jann Yang, Ramalingam Sridhar, Victor Demjanenko:
Parallel Intersecting Compressed Bit Vectors in a High Speed Query Server for Processing Postal Addresses. 232-241
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Caches

Brad Calder, Dirk Grunwald, Joel S. Emer:
Predictive Sequential Associative Cache. 244-253
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Thomas Alexander, Gershon Kedem:
Distributed Prefetch-buffer/Cache Design for High-Performance Memory Systems. 254-263
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High-Performance Processors

Zarka Cvetanovic, Dileep Bhandarkar:
Performance Characterization of the Alpha 21164 Microprocessor Using TP and SPEC Workloads. 270-280
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Roger Espasa, Mateo Valero:
Decoupled Vector Architectures. 281-290
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Manu Gulati, Nader Bagherzadeh:
Performance Study of a Multithreaded Superscalar Microprocessor. 291-301
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Cache Protocols

Craig Anderson, Anna R. Karlin:
Two Adaptive Hybrid Cache Coherency Protocols. 303-313
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Masafumi Takahashi, Hiroyuki Takano, Emi Kaneko, Seigo Suzuki:
A Shared-Bus Control Mechanism and a Cache Coherence Protocol for a High-Performance On-Chip Multiprocessor. 314-322
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Alain Raynaud, Zheng Zhang, Josep Torrellas:
Distance-Adaptive Update Protocols for Scalable Shared-Memory Multiprocessors. 323-334
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