| 2008 |
|---|
| 9 | EE | Pedro A. Castillo,
Antonio Miguel Mora,
Juan Julián Merelo Guervós,
Juan Luís Jiménez Laredo,
Miquel Moretó,
Francisco J. Cazorla,
Mateo Valero,
Sally A. McKee:
Architecture Performance Prediction Using Evolutionary Artificial Neural Networks.
EvoWorkshops 2008: 175-183 |
| 8 | EE | Miquel Moretó,
Francisco J. Cazorla,
Alex Ramírez,
Mateo Valero:
MLP-Aware Dynamic Cache Partitioning.
HiPEAC 2008: 337-352 |
| 7 | EE | Pedro A. Castillo Valdivieso,
Juan Julián Merelo Guervós,
Miquel Moretó,
Francisco J. Cazorla,
Mateo Valero,
Antonio Miguel Mora,
Juan Luís Jiménez Laredo,
Sally A. McKee:
Evolutionary system for prediction and optimization of hardware architecture performance.
IEEE Congress on Evolutionary Computation 2008: 1941-1948 |
| 6 | EE | Carmen Martínez,
Ramón Beivide,
E. Stafford,
Miquel Moretó,
Ernst M. Gabidulin:
Modeling Toroidal Networks with the Gaussian Integers.
IEEE Trans. Computers 57(8): 1046-1056 (2008) |
| 2007 |
|---|
| 5 | EE | Miquel Moretó,
Francisco J. Cazorla,
Alex Ramírez,
Mateo Valero:
Online Prediction of Applications Cache Utility.
ICSAMOS 2007: 169-177 |
| 4 | EE | Jose M. Camara,
Miquel Moretó,
Enrique Vallejo,
Ramón Beivide,
José Miguel-Alonso,
Carmen Martínez,
Javier Navaridas:
Mixed-radix Twisted Torus Interconnection Networks.
IPDPS 2007: 1-10 |
| 3 | EE | Miquel Moretó,
Francisco J. Cazorla,
Alex Ramírez,
Mateo Valero:
MLP-Aware Dynamic Cache Partitioning.
PACT 2007: 418 |
| 2 | EE | Miquel Moretó,
Francisco J. Cazorla,
Alex Ramírez,
Mateo Valero:
Explaining Dynamic Cache Partitioning Speed Ups.
Computer Architecture Letters 6(1): 1-4 (2007) |
| 2006 |
|---|
| 1 | EE | Carmen Martínez,
Enrique Vallejo,
Ramón Beivide,
Cruz Izu,
Miquel Moretó:
Dense Gaussian Networks: Suitable Topologies for On-Chip Multiprocessors.
International Journal of Parallel Programming 34(3): 193-211 (2006) |
