Francisco J. Cazorla

2008
26	EE	Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Mateo Valero: Soft Real-Time Scheduling on SMT Processors with Explicit Resource Allocation. ARCS 2008: 173-187
25	EE	Pedro A. Castillo, Antonio Miguel Mora, Juan Julián Merelo Guervós, Juan Luís Jiménez Laredo, Miquel Moretó, Francisco J. Cazorla, Mateo Valero, Sally A. McKee: Architecture Performance Prediction Using Evolutionary Artificial Neural Networks. EvoWorkshops 2008: 175-183
24	EE	Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero: MLP-Aware Dynamic Cache Partitioning. HiPEAC 2008: 337-352
23	EE	Carmelo Acosta, Francisco J. Cazorla, Alex Ramírez, Mateo Valero: MFLUSH: Handling Long-Latency Loads in SMT On-Chip Multiprocessors. ICPP 2008: 173-181
22	EE	Pedro A. Castillo Valdivieso, Juan Julián Merelo Guervós, Miquel Moretó, Francisco J. Cazorla, Mateo Valero, Antonio Miguel Mora, Juan Luís Jiménez Laredo, Sally A. McKee: Evolutionary system for prediction and optimization of hardware architecture performance. IEEE Congress on Evolutionary Computation 2008: 1941-1948
21	EE	Carlos Boneti, Roberto Gioiosa, Francisco J. Cazorla, Julita Corbalán, Jesús Labarta, Mateo Valero: Balancing HPC applications through smart allocation of resources in MT processors. IPDPS 2008: 1-12
20	EE	Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Ruden González, Alexander V. Veidenbaum, Daniel A. Jiménez, Mateo Valero: A Two-Level Load/Store Queue Based on Execution Locality. ISCA 2008: 25-36
19	EE	Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Chen-Yong Cher, Mateo Valero: Software-Controlled Priority Characterization of POWER5 Processor. ISCA 2008: 415-426
18	EE	Carlos Boneti, Roberto Gioiosa, Francisco J. Cazorla, Mateo Valero: A dynamic scheduler for balancing HPC applications. SC 2008: 41
2007
17	EE	Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero: Online Prediction of Applications Cache Utility. ICSAMOS 2007: 169-177
16	EE	Francisco J. Cazorla, Enrique Fernández, Peter M. W. Knijnenburg, Alex Ramírez, Rizos Sakellariou, Mateo Valero: On the Problem of Minimizing Workload Execution Time in SMT Processors. ICSAMOS 2007: 66-73
15	EE	Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Ruben Gonzalez, Daniel A. Jiménez, Mateo Valero: A Flexible Heterogeneous Multi-Core Architecture. PACT 2007: 13-24
14	EE	Javier Vera, Francisco J. Cazorla, Alex Pajuelo, Oliverio J. Santana, Enrique Fernández, Mateo Valero: FAME: FAirly MEasuring Multithreaded Architectures. PACT 2007: 305-316
13	EE	Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero: MLP-Aware Dynamic Cache Partitioning. PACT 2007: 418
12	EE	Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero: Explaining Dynamic Cache Partitioning Speed Ups. Computer Architecture Letters 6(1): 1-4 (2007)
2006
11	EE	Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero: Predictable Performance in SMT Processors: Synergy between the OS and SMTs. IEEE Trans. Computers 55(7): 785-799 (2006)
2005
10	EE	Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero: Architectural support for real-time task scheduling in SMT processors. CASES 2005: 166-176
9	EE	Adrián Cristal, Oliverio J. Santana, Francisco J. Cazorla, Marco Galluzzi, Tanausú Ramírez, Miquel Pericàs, Mateo Valero: Kilo-Instruction Processors: Overcoming the Memory Wall. IEEE Micro 25(3): 48-57 (2005)
2004
8	EE	Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero: Predictable performance in SMT processors. Conf. Computing Frontiers 2004: 433-443
7	EE	Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero: Implicit vs. Explicit Resource Allocation in SMT Processors. DSD 2004: 44-51
6	EE	Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero: Feasibility of QoS for SMT. Euro-Par 2004: 535-540
5	EE	Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández: DCache Warn: An I-Fetch Policy to Increase SMT Efficiency. IPDPS 2004
4	EE	Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández: Dynamically Controlled Resource Allocation in SMT Processors. MICRO 2004: 171-182
3	EE	Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández: QoS for High-Performance SMT Processors in Embedded Systems. IEEE Micro 24(4): 24-31 (2004)
2	EE	Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández: Optimising long-latency-load-aware fetch policies for SMT processors. IJHPCN 2(1): 45-54 (2004)
2003
1	EE	Francisco J. Cazorla, Enrique Fernández, Alex Ramírez, Mateo Valero: Improving Memory Latency Aware Fetch Policies for SMT Processors. ISHPC 2003: 70-85

Coauthor Index

1	Carmelo Acosta	[23]
2	Carlos Boneti	[18] [19] [21] [26]
3	Alper Buyuktosunoglu	[19]
4	Chen-Yong Cher	[19]
5	Julita Corbalán	[21]
6	Adrián Cristal	[9] [15] [20]
7	Enrique Fernández	[1] [2] [3] [4] [5] [6] [7] [8] [10] [11] [14] [16]
8	Marco Galluzzi	[9]
9	Roberto Gioiosa	[18] [19] [21] [26]
10	Ruben Gonzalez	[15]
11	Ruden González	[20]
12	Juan Julián Merelo Guervós (Juan J. Merelo Guervós)	[22] [25]
13	Daniel A. Jiménez	[15] [20]
14	Peter M. W. Knijnenburg	[3] [6] [7] [8] [10] [11] [16]
15	Jesús Labarta	[21]
16	Juan Luís Jiménez Laredo	[22] [25]
17	Sally A. McKee	[22] [25]
18	Antonio Miguel Mora	[22] [25]
19	Miquel Moretó	[12] [13] [17] [22] [24] [25]
20	Alex Pajuelo	[14]
21	Miquel Pericàs	[9] [15] [20]
22	Alex Ramírez	[1] [2] [3] [4] [5] [6] [7] [8] [10] [11] [12] [13] [16] [17] [23] [24]
23	Tanausú Ramírez	[9]
24	Rizos Sakellariou	[3] [6] [7] [8] [10] [11] [16]
25	Oliverio J. Santana	[9] [14]
26	Pedro A. Castillo Valdivieso (Pedro A. Castillo)	[22] [25]
27	Mateo Valero	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26]
28	Alexander V. Veidenbaum	[20]
29	Javier Vera	[14]