31. ISCA 2004:
Munich,
Germany
31st International Symposium on Computer Architecture (ISCA 2004), 19-23 June 2004, Munich, Germany.
IEEE Computer Society 2004, ISBN 0-7695-2143-6 BibTeX
@proceedings{DBLP:conf/isca/2004,
title = {31st International Symposium on Computer Architecture (ISCA 2004),
19-23 June 2004, Munich, Germany},
booktitle = {ISCA},
publisher = {IEEE Computer Society},
year = {2004},
isbn = {0-7695-2143-6},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Architecture Evaluations
- Michael Bedford Taylor, Walter Lee, Jason E. Miller, David Wentzlaff, Ian Bratt, Ben Greenwald, Henry Hoffmann, Paul Johnson, Jason Sungtae Kim, James Psota, Arvind Saraf, Nathan Shnidman, Volker Strumpen, Matthew Frank, Saman P. Amarasinghe, Anant Agarwal:
Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams.
2-13
Electronic Edition (link) BibTeX
- Jung Ho Ahn, William J. Dally, Brucek Khailany, Ujval J. Kapasi, Abhishek Das:
Evaluating the Imagine Stream Architecture.
14-25
Electronic Edition (link) BibTeX
- John W. Sias, Sain-Zee Ueng, Geoff A. Kent, Ian M. Steiner, Erik M. Nystrom, Wen-mei W. Hwu:
Field-testing IMPACT EPIC research results in Itanium 2.
26-39
Electronic Edition (link) BibTeX
Parallelism in Microarchitectures
- T. N. Vijaykumar, Zeshan Chishti:
Wire Delay is Not a Problem for SMT (In the Near Future).
40-51
Electronic Edition (link) BibTeX
- Ronny Krashinsky, Christopher Batten, Mark Hampton, Steve Gerding, Brian Pharris, Jared Casper, Krste Asanovic:
The Vector-Thread Architecture.
52-63
Electronic Edition (link) BibTeX
- Rakesh Kumar, Dean M. Tullsen, Parthasarathy Ranganathan, Norman P. Jouppi, Keith I. Farkas:
Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance.
64-75
Electronic Edition (link) BibTeX
- Yuan Chou, Brian Fahs, Santosh G. Abraham:
Microarchitecture Optimizations for Exploiting Memory-Level Parallelism.
76-89
Electronic Edition (link) BibTeX
Memory Consistency
- Harold W. Cain, Mikko H. Lipasti:
Memory Ordering: A Value-Based Approach.
90-101
Electronic Edition (link) BibTeX
- Lance Hammond, Vicky Wong, Michael K. Chen, Brian D. Carlstrom, John D. Davis, Ben Hertzberg, Manohar K. Prabhu, Honggo Wijaya, Christos Kozyrakis, Kunle Olukotun:
Transactional Memory Coherence and Consistency.
102-113
Electronic Edition (link) BibTeX
- Sudheendra Hangal, Durgam Vahia, Chaiyasit Manovit, Juin-Yeu Joseph Lu, Sridhar Narayanan:
TSOtool: A Program for Verifying Memory Systems Using the Memory Consistency Model.
114-123
Electronic Edition (link) BibTeX
- Mainak Chaudhuri, Mark Heinrich:
SMTp: An Architecture for Next-generation Scalable Multi-threading.
124-137
Electronic Edition (link) BibTeX
Power and Energy
- Christopher J. Hughes, Sarita V. Adve:
A Formal Approach to Frequent Energy Adaptations for Multimedia Applications.
138-149
Electronic Edition (link) BibTeX
- John Oliver, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones IV, Diana Franklin, Venkatesh Akella, Frederic T. Chong:
Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor.
150-161
Electronic Edition (link) BibTeX
- Roni Rosner, Yoav Almog, Micha Moffie, Naftali Schwartz, Avi Mendelson:
Power Awareness through Selective Dynamically Optimized Traces.
162-175
Electronic Edition (link) BibTeX
Interconnect and I/O
Compression and Debugging
Superscalars
Support for Reliability
Register File
Performance Methodologies
Microarchitectural Concepts
Copyright © Sat May 16 23:24:58 2009
by Michael Ley (ley@uni-trier.de)
